[u-boot.git] / board / engicam / icorem6_rqs / icorem6_rqs.c

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const uart4_pads[] = {
	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};

int board_early_init_f(void)
{
	SETUP_IOMUX_PADS(uart4_pads);

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	return 0;
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>

#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>

/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const usdhc3_pads[] = {
	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC3_BASE_ADDR, 1, 4},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC3_BASE_ADDR:
		ret = 1;
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int i, ret;

	/*
	* According to the board_mmc_init() the following map is done:
	* (U-boot device node)    (Physical Port)
	* mmc0				USDHC3
	*/
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			SETUP_IOMUX_PADS(usdhc3_pads);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		default:
			printf("Warning - USDHC%d controller not supporting\n",
			       i + 1);
			return 0;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
}

#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
	u32 bmode = imx6_src_get_boot_mode();
	u8 boot_dev = BOOT_DEVICE_MMC1;

	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	case IMX6_BMODE_SD:
	case IMX6_BMODE_ESD:
		/* SD/eSD - BOOT_DEVICE_MMC1 */
		break;
	case IMX6_BMODE_MMC:
	case IMX6_BMODE_EMMC:
		/* MMC/eMMC */
		boot_dev = BOOT_DEVICE_MMC2;
		break;
	default:
		/* Default - BOOT_DEVICE_MMC1 */
		printf("Wrong board boot order\n");
		break;
	}

	spl_boot_list[0] = boot_dev;
}
#endif
#endif

/*
 * Driving strength:
 *   0x30 == 40 Ohm
 *   0x28 == 48 Ohm
 */

#define IMX6DQ_DRIVE_STRENGTH		0x30
#define IMX6SDL_DRIVE_STRENGTH		0x28

/* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	.dram_sdqs0 = 0x28,
	.dram_sdqs1 = 0x28,
	.dram_sdqs2 = 0x28,
	.dram_sdqs3 = 0x28,
	.dram_sdqs4 = 0x28,
	.dram_sdqs5 = 0x28,
	.dram_sdqs6 = 0x28,
	.dram_sdqs7 = 0x28,
	.dram_dqm0 = 0x28,
	.dram_dqm1 = 0x28,
	.dram_dqm2 = 0x28,
	.dram_dqm3 = 0x28,
	.dram_dqm4 = 0x28,
	.dram_dqm5 = 0x28,
	.dram_dqm6 = 0x28,
	.dram_dqm7 = 0x28,
	.dram_cas = 0x30,
	.dram_ras = 0x30,
	.dram_sdclk_0 = 0x30,
	.dram_sdclk_1 = 0x30,
	.dram_reset = 0x30,
	.dram_sdcke0 = 0x3000,
	.dram_sdcke1 = 0x3000,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = 0x30,
	.dram_sdodt1 = 0x30,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	.grp_b0ds = 0x30,
	.grp_b1ds = 0x30,
	.grp_b2ds = 0x30,
	.grp_b3ds = 0x30,
	.grp_b4ds = 0x30,
	.grp_b5ds = 0x30,
	.grp_b6ds = 0x30,
	.grp_b7ds = 0x30,
	.grp_addds = 0x30,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_ddrmode = 0x00020000,
	.grp_ctlds = 0x30,
	.grp_ddr_type = 0x000c0000,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	.dram_sdclk_0 = 0x30,
	.dram_sdclk_1 = 0x30,
	.dram_cas = 0x30,
	.dram_ras = 0x30,
	.dram_reset = 0x30,
	.dram_sdcke0 = 0x30,
	.dram_sdcke1 = 0x30,
	.dram_sdba2 = 0x00000000,
	.dram_sdodt0 = 0x30,
	.dram_sdodt1 = 0x30,
	.dram_sdqs0 = 0x28,
	.dram_sdqs1 = 0x28,
	.dram_sdqs2 = 0x28,
	.dram_sdqs3 = 0x28,
	.dram_sdqs4 = 0x28,
	.dram_sdqs5 = 0x28,
	.dram_sdqs6 = 0x28,
	.dram_sdqs7 = 0x28,
	.dram_dqm0 = 0x28,
	.dram_dqm1 = 0x28,
	.dram_dqm2 = 0x28,
	.dram_dqm3 = 0x28,
	.dram_dqm4 = 0x28,
	.dram_dqm5 = 0x28,
	.dram_dqm6 = 0x28,
	.dram_dqm7 = 0x28,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	.grp_ddrpke = 0x00000000,
	.grp_addds = 0x30,
	.grp_ctlds = 0x30,
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x28,
	.grp_b1ds = 0x28,
	.grp_b2ds = 0x28,
	.grp_b3ds = 0x28,
	.grp_b4ds = 0x28,
	.grp_b5ds = 0x28,
	.grp_b6ds = 0x28,
	.grp_b7ds = 0x28,
};

/* mt41j256 */
static struct mx6_ddr3_cfg mt41j256 = {
	.mem_speed = 1066,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 13,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
	.SRT = 0,
};

static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
	.p0_mpwldectrl0 = 0x000E0009,
	.p0_mpwldectrl1 = 0x0018000E,
	.p1_mpwldectrl0 = 0x00000007,
	.p1_mpwldectrl1 = 0x00000000,
	.p0_mpdgctrl0 = 0x43280334,
	.p0_mpdgctrl1 = 0x031C0314,
	.p1_mpdgctrl0 = 0x4318031C,
	.p1_mpdgctrl1 = 0x030C0258,
	.p0_mprddlctl = 0x3E343A40,
	.p1_mprddlctl = 0x383C3844,
	.p0_mpwrdlctl = 0x40404440,
	.p1_mpwrdlctl = 0x4C3E4446,
};

/* DDR 64bit */
static struct mx6_ddr_sysinfo mem_q = {
	.ddr_type	= DDR_TYPE_DDR3,
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 2,
	.rtt_wr		= 2,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
	.p0_mpwldectrl0 = 0x001F0024,
	.p0_mpwldectrl1 = 0x00110018,
	.p1_mpwldectrl0 = 0x001F0024,
	.p1_mpwldectrl1 = 0x00110018,
	.p0_mpdgctrl0 = 0x4230022C,
	.p0_mpdgctrl1 = 0x02180220,
	.p1_mpdgctrl0 = 0x42440248,
	.p1_mpdgctrl1 = 0x02300238,
	.p0_mprddlctl = 0x44444A48,
	.p1_mprddlctl = 0x46484A42,
	.p0_mpwrdlctl = 0x38383234,
	.p1_mpwrdlctl = 0x3C34362E,
};

/* DDR 64bit 1GB */
static struct mx6_ddr_sysinfo mem_dl = {
	.dsize		= 2,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 1,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

/* DDR 32bit 512MB */
static struct mx6_ddr_sysinfo mem_s = {
	.dsize		= 1,
	.cs1_mirror	= 0,
	/* config for full 4GB range so that get_mem_size() works */
	.cs_density	= 32,
	.ncs		= 1,
	.bi_on		= 1,
	.rtt_nom	= 1,
	.rtt_wr		= 1,
	.ralat		= 5,
	.walat		= 0,
	.mif3_mode	= 3,
	.rst_to_cke	= 0x23,
	.sde_to_rst	= 0x10,
};

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00003F3F, &ccm->CCGR0);
	writel(0x0030FC00, &ccm->CCGR1);
	writel(0x000FC000, &ccm->CCGR2);
	writel(0x3F300000, &ccm->CCGR3);
	writel(0xFF00F300, &ccm->CCGR4);
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003CC, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

static void spl_dram_init(void)
{
	if (is_mx6solo()) {
		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
	} else if (is_mx6dl()) {
		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
	} else if (is_mx6dq()) {
		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
	}

	udelay(100);
}

void board_init_f(ulong dummy)
{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	gpr_init();

	/* iomux */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif
Commit	Line	Data
871ec6da JT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10
	11	#include <asm/io.h>
	12	#include <asm/gpio.h>
	13	#include <linux/sizes.h>
	14
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/crm_regs.h>
	17	#include <asm/arch/iomux.h>
	18	#include <asm/arch/mx6-pins.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/imx-common/iomux-v3.h>
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
	24	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	25	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	26	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	27
	28	static iomux_v3_cfg_t const uart4_pads[] = {
	29	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	30	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	31	};
	32
	33	int board_early_init_f(void)
	34	{
	35	SETUP_IOMUX_PADS(uart4_pads);
	36
	37	return 0;
	38	}
	39
	40	int board_init(void)
	41	{
	42	/* Address of boot parameters */
	43	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	44
	45	return 0;
	46	}
	47
	48	int dram_init(void)
	49	{
	50	gd->ram_size = imx_ddr_size();
	51
	52	return 0;
	53	}
	54
	55	#ifdef CONFIG_SPL_BUILD
	56	#include <libfdt.h>
	57	#include <spl.h>
	58
	59	#include <asm/arch/crm_regs.h>
	60	#include <asm/arch/mx6-ddr.h>
	61
	62	/* MMC board initialization is needed till adding DM support in SPL */
	63	#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
	64	#include <mmc.h>
65	#include <fsl_esdhc.h>
66
67	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
68	PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_HIGH \| \
69	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
70
71	static iomux_v3_cfg_t const usdhc3_pads[] = {
72	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78	};
79
80	struct fsl_esdhc_cfg usdhc_cfg[1] = {
81	{USDHC3_BASE_ADDR, 1, 4},
82	};
83
84	int board_mmc_getcd(struct mmc *mmc)
85	{
86	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
87	int ret = 0;
88
89	switch (cfg->esdhc_base) {
90	case USDHC3_BASE_ADDR:
91	ret = 1;
92	break;
93	}
94
95	return ret;
96	}
97
98	int board_mmc_init(bd_t *bis)
99	{
100	int i, ret;
101
102	/*
103	* According to the board_mmc_init() the following map is done:
104	* (U-boot device node) (Physical Port)
105	* mmc0 USDHC3
106	*/
107	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
108	switch (i) {
109	case 0:
110	SETUP_IOMUX_PADS(usdhc3_pads);
111	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
112	break;
113	default:
114	printf("Warning - USDHC%d controller not supporting\n",
115	i + 1);
116	return 0;
117	}
118
119	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
120	if (ret) {
121	printf("Warning: failed to initialize mmc dev %d\n", i);
122	return ret;
123	}
124	}
125
126	return 0;
127	}
10fa3ee0 JT	128
	129	#ifdef CONFIG_ENV_IS_IN_MMC
	130	void board_boot_order(u32 *spl_boot_list)
	131	{
	132	u32 bmode = imx6_src_get_boot_mode();
	133	u8 boot_dev = BOOT_DEVICE_MMC1;
	134
	135	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	136	case IMX6_BMODE_SD:
	137	case IMX6_BMODE_ESD:
	138	/* SD/eSD - BOOT_DEVICE_MMC1 */
	139	break;
	140	case IMX6_BMODE_MMC:
	141	case IMX6_BMODE_EMMC:
	142	/* MMC/eMMC */
	143	boot_dev = BOOT_DEVICE_MMC2;
	144	break;
	145	default:
	146	/* Default - BOOT_DEVICE_MMC1 */
	147	printf("Wrong board boot order\n");
	148	break;
	149	}
	150
	151	spl_boot_list[0] = boot_dev;
	152	}
	153	#endif
871ec6da JT	154	#endif
	155
	156	/*
	157	* Driving strength:
	158	* 0x30 == 40 Ohm
	159	* 0x28 == 48 Ohm
	160	*/
	161
	162	#define IMX6DQ_DRIVE_STRENGTH 0x30
	163	#define IMX6SDL_DRIVE_STRENGTH 0x28
	164
	165	/* configure MX6Q/DUAL mmdc DDR io registers */
	166	static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	167	.dram_sdqs0 = 0x28,
	168	.dram_sdqs1 = 0x28,
	169	.dram_sdqs2 = 0x28,
	170	.dram_sdqs3 = 0x28,
	171	.dram_sdqs4 = 0x28,
	172	.dram_sdqs5 = 0x28,
	173	.dram_sdqs6 = 0x28,
	174	.dram_sdqs7 = 0x28,
	175	.dram_dqm0 = 0x28,
	176	.dram_dqm1 = 0x28,
	177	.dram_dqm2 = 0x28,
	178	.dram_dqm3 = 0x28,
	179	.dram_dqm4 = 0x28,
	180	.dram_dqm5 = 0x28,
	181	.dram_dqm6 = 0x28,
	182	.dram_dqm7 = 0x28,
	183	.dram_cas = 0x30,
	184	.dram_ras = 0x30,
	185	.dram_sdclk_0 = 0x30,
	186	.dram_sdclk_1 = 0x30,
	187	.dram_reset = 0x30,
	188	.dram_sdcke0 = 0x3000,
	189	.dram_sdcke1 = 0x3000,
	190	.dram_sdba2 = 0x00000000,
	191	.dram_sdodt0 = 0x30,
	192	.dram_sdodt1 = 0x30,
	193	};
	194
	195	/* configure MX6Q/DUAL mmdc GRP io registers */
	196	static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	197	.grp_b0ds = 0x30,
	198	.grp_b1ds = 0x30,
	199	.grp_b2ds = 0x30,
	200	.grp_b3ds = 0x30,
	201	.grp_b4ds = 0x30,
	202	.grp_b5ds = 0x30,
	203	.grp_b6ds = 0x30,
	204	.grp_b7ds = 0x30,
	205	.grp_addds = 0x30,
	206	.grp_ddrmode_ctl = 0x00020000,
	207	.grp_ddrpke = 0x00000000,
	208	.grp_ddrmode = 0x00020000,
	209	.grp_ctlds = 0x30,
	210	.grp_ddr_type = 0x000c0000,
	211	};
	212
	213	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	214	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	215	.dram_sdclk_0 = 0x30,
	216	.dram_sdclk_1 = 0x30,
	217	.dram_cas = 0x30,
218	.dram_ras = 0x30,
219	.dram_reset = 0x30,
220	.dram_sdcke0 = 0x30,
221	.dram_sdcke1 = 0x30,
222	.dram_sdba2 = 0x00000000,
223	.dram_sdodt0 = 0x30,
224	.dram_sdodt1 = 0x30,
225	.dram_sdqs0 = 0x28,
226	.dram_sdqs1 = 0x28,
227	.dram_sdqs2 = 0x28,
228	.dram_sdqs3 = 0x28,
229	.dram_sdqs4 = 0x28,
230	.dram_sdqs5 = 0x28,
231	.dram_sdqs6 = 0x28,
232	.dram_sdqs7 = 0x28,
233	.dram_dqm0 = 0x28,
234	.dram_dqm1 = 0x28,
235	.dram_dqm2 = 0x28,
236	.dram_dqm3 = 0x28,
237	.dram_dqm4 = 0x28,
238	.dram_dqm5 = 0x28,
239	.dram_dqm6 = 0x28,
240	.dram_dqm7 = 0x28,
241	};
242
243	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
244	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
245	.grp_ddr_type = 0x000c0000,
246	.grp_ddrmode_ctl = 0x00020000,
247	.grp_ddrpke = 0x00000000,
248	.grp_addds = 0x30,
249	.grp_ctlds = 0x30,
250	.grp_ddrmode = 0x00020000,
251	.grp_b0ds = 0x28,
252	.grp_b1ds = 0x28,
253	.grp_b2ds = 0x28,
254	.grp_b3ds = 0x28,
255	.grp_b4ds = 0x28,
256	.grp_b5ds = 0x28,
257	.grp_b6ds = 0x28,
258	.grp_b7ds = 0x28,
259	};
260
261	/* mt41j256 */
262	static struct mx6_ddr3_cfg mt41j256 = {
263	.mem_speed = 1066,
264	.density = 2,
265	.width = 16,
266	.banks = 8,
267	.rowaddr = 13,
268	.coladdr = 10,
269	.pagesz = 2,
270	.trcd = 1375,
271	.trcmin = 4875,
272	.trasmin = 3500,
273	.SRT = 0,
274	};
275
276	static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
277	.p0_mpwldectrl0 = 0x000E0009,
278	.p0_mpwldectrl1 = 0x0018000E,
279	.p1_mpwldectrl0 = 0x00000007,
280	.p1_mpwldectrl1 = 0x00000000,
281	.p0_mpdgctrl0 = 0x43280334,
282	.p0_mpdgctrl1 = 0x031C0314,
283	.p1_mpdgctrl0 = 0x4318031C,
284	.p1_mpdgctrl1 = 0x030C0258,
285	.p0_mprddlctl = 0x3E343A40,
286	.p1_mprddlctl = 0x383C3844,
287	.p0_mpwrdlctl = 0x40404440,
288	.p1_mpwrdlctl = 0x4C3E4446,
289	};
290
291	/* DDR 64bit */
292	static struct mx6_ddr_sysinfo mem_q = {
293	.ddr_type = DDR_TYPE_DDR3,
294	.dsize = 2,
295	.cs1_mirror = 0,
296	/* config for full 4GB range so that get_mem_size() works */
297	.cs_density = 32,
298	.ncs = 1,
299	.bi_on = 1,
300	.rtt_nom = 2,
301	.rtt_wr = 2,
302	.ralat = 5,
303	.walat = 0,
304	.mif3_mode = 3,
305	.rst_to_cke = 0x23,
306	.sde_to_rst = 0x10,
307	};
308
309	static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
310	.p0_mpwldectrl0 = 0x001F0024,
311	.p0_mpwldectrl1 = 0x00110018,
312	.p1_mpwldectrl0 = 0x001F0024,
313	.p1_mpwldectrl1 = 0x00110018,
314	.p0_mpdgctrl0 = 0x4230022C,
315	.p0_mpdgctrl1 = 0x02180220,
316	.p1_mpdgctrl0 = 0x42440248,
317	.p1_mpdgctrl1 = 0x02300238,
318	.p0_mprddlctl = 0x44444A48,
319	.p1_mprddlctl = 0x46484A42,
320	.p0_mpwrdlctl = 0x38383234,
321	.p1_mpwrdlctl = 0x3C34362E,
322	};
323
324	/* DDR 64bit 1GB */
325	static struct mx6_ddr_sysinfo mem_dl = {
326	.dsize = 2,
327	.cs1_mirror = 0,
328	/* config for full 4GB range so that get_mem_size() works */
329	.cs_density = 32,
330	.ncs = 1,
331	.bi_on = 1,
332	.rtt_nom = 1,
333	.rtt_wr = 1,
334	.ralat = 5,
335	.walat = 0,
336	.mif3_mode = 3,
337	.rst_to_cke = 0x23,
338	.sde_to_rst = 0x10,
339	};
340
341	/* DDR 32bit 512MB */
342	static struct mx6_ddr_sysinfo mem_s = {
343	.dsize = 1,
344	.cs1_mirror = 0,
345	/* config for full 4GB range so that get_mem_size() works */
346	.cs_density = 32,
347	.ncs = 1,
348	.bi_on = 1,
349	.rtt_nom = 1,
350	.rtt_wr = 1,
351	.ralat = 5,
352	.walat = 0,
353	.mif3_mode = 3,
354	.rst_to_cke = 0x23,
355	.sde_to_rst = 0x10,
356	};
357
358	static void ccgr_init(void)
359	{
360	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
361
362	writel(0x00003F3F, &ccm->CCGR0);
363	writel(0x0030FC00, &ccm->CCGR1);
364	writel(0x000FC000, &ccm->CCGR2);
365	writel(0x3F300000, &ccm->CCGR3);
366	writel(0xFF00F300, &ccm->CCGR4);
367	writel(0x0F0000C3, &ccm->CCGR5);
368	writel(0x000003CC, &ccm->CCGR6);
369	}
370
371	static void gpr_init(void)
372	{
373	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
374
375	/* enable AXI cache for VDOA/VPU/IPU */
376	writel(0xF00000CF, &iomux->gpr[4]);
377	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
378	writel(0x007F007F, &iomux->gpr[6]);
379	writel(0x007F007F, &iomux->gpr[7]);
380	}
381
382	static void spl_dram_init(void)
383	{
384	if (is_mx6solo()) {
385	mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
386	mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
387	} else if (is_mx6dl()) {
388	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
389	mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
390	} else if (is_mx6dq()) {
391	mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
392	mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
393	}
394
395	udelay(100);
396	}
397
398	void board_init_f(ulong dummy)
399	{
400	ccgr_init();
401
402	/* setup AIPS and disable watchdog */
403	arch_cpu_init();
404
405	gpr_init();
406
407	/* iomux */
408	board_early_init_f();
409
410	/* setup GP timer */
411	timer_init();
412
413	/* UART clocks enabled and gd valid - init serial console */
414	preloader_console_init();
415
416	/* DDR initialization */
417	spl_dram_init();
418
419	/* Clear the BSS. */
420	memset(__bss_start, 0, __bss_end - __bss_start);
421
422	/* load/boot image from boot device */
423	board_init_r(NULL, 0);
424	}
425	#endif