[thirdparty/u-boot.git] / board / ep82xxm / ep82xxm.c

/*
 * Copyright (C) 2006 Embedded Planet, LLC.
 *
 * Support for Embedded Planet EP82xxM boards.
 * Tested on EP82xxM (MPC8270).
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc8260.h>
#include <ioports.h>
#include <asm/m8260_pci.h>
#ifdef CONFIG_PCI
#include <pci.h>
#endif
#include <miiphy.h>
#include <linux/compiler.h>

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

#define CONFIG_SYS_FCC2 1
#define CONFIG_SYS_FCC3 1

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A */
    {	/*	     conf      ppar psor pdir podr pdat */
	/* PA31 */ { 0,		 0,   0,   0,	0,   1 }, /* PA31	     */
	/* PA30 */ { 0,		 0,   0,   0,	0,   1 }, /* PA30	     */
	/* PA29 */ { 0,		 0,   0,   0,	0,   1 }, /* PA29	     */
	/* PA28 */ { 0,		 0,   0,   0,	0,   1 }, /* PA28	     */
	/* PA27 */ { 0,		 0,   0,   0,	0,   1 }, /* PA27	     */
	/* PA26 */ { 0,		 0,   0,   0,	0,   1 }, /* PA26	     */
	/* PA25 */ { 0,		 0,   0,   0,	0,   1 }, /* PA25	     */
	/* PA24 */ { 0,		 0,   0,   0,	0,   1 }, /* PA24	     */
	/* PA23 */ { 0,		 0,   0,   0,	0,   1 }, /* PA23	     */
	/* PA22 */ { 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
	/* PA21 */ { 0,		 0,   0,   0,	0,   1 }, /* PA21	     */
	/* PA20 */ { 0,		 0,   0,   0,	0,   1 }, /* PA20	     */
	/* PA19 */ { 0,		 0,   0,   0,	0,   1 }, /* PA19	     */
	/* PA18 */ { 0,		 0,   0,   0,	0,   1 }, /* PA18	     */
	/* PA17 */ { 0,		 0,   0,   0,	0,   1 }, /* PA17	     */
	/* PA16 */ { 0,		 0,   0,   0,	0,   1 }, /* PA16	     */
	/* PA15 */ { 0,		 0,   0,   0,	0,   1 }, /* PA15	     */
	/* PA14 */ { 0,		 0,   0,   0,	0,   1 }, /* PA14	     */
	/* PA13 */ { 0,		 0,   0,   0,	0,   1 }, /* PA13	     */
	/* PA12 */ { 0,		 0,   0,   0,	0,   1 }, /* PA12	     */
	/* PA11 */ { 0,		 0,   0,   0,	0,   1 }, /* PA11	     */
	/* PA10 */ { 0,		 0,   0,   0,	0,   1 }, /* PA10	     */
	/* PA9	*/ { 1,		 1,   0,   1,	0,   1 }, /* SMC2 TxD	     */
	/* PA8	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC2 RxD	     */
	/* PA7	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA7	     */
	/* PA6	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA6	     */
	/* PA5	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA5	     */
	/* PA4	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA4	     */
	/* PA3	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA3	     */
	/* PA2	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA2	     */
	/* PA1	*/ { 0,		 0,   0,   0,	0,   1 }, /* PA1	     */
	/* PA0	*/ { 0,		 0,   0,   0,	0,   1 }  /* PA0	     */
    },

    /* Port B */
    {	/*	     conf	ppar psor pdir podr pdat */
	/* PB31 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TX_ER  */
	/* PB30 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_DV  */
	/* PB29 */ { CONFIG_SYS_FCC2,	 1,   1,   1,	0,   0 }, /* FCC2 MII TX_EN  */
	/* PB28 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_ER  */
	/* PB27 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII COL    */
	/* PB26 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII CRS    */
	/* PB25 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[3] */
	/* PB24 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[2] */
	/* PB23 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[1] */
	/* PB22 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[0] */
	/* PB21 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[0] */
	/* PB20 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[1] */
	/* PB19 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[2] */
	/* PB18 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[3] */
	/* PB17 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_DIV     */
	/* PB16 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_ERR     */
	/* PB15 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_ERR     */
	/* PB14 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_EN      */
	/* PB13 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:COL	     */
	/* PB12 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:CRS	     */
	/* PB11 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
	/* PB10 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
	/* PB9	*/ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
	/* PB8	*/ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PB7	     */
	/* PB6	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
	/* PB5	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
	/* PB4	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
    },

    /* Port C */
    {	/*	     conf	ppar psor pdir podr pdat */
	/* PC31 */ { 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
	/* PC29 */ { 1,		 1,   1,   0,	0,   0 }, /* SCC1 CTS#	     */
	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
	/* PC27 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3: TXD[0]    */
	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
	/* PC25 */ { 0,		 0,   0,   0,	0,   0 }, /* PC25	     */
	/* PC24 */ { 0,		 0,   0,   0,	0,   0 }, /* PC24	     */
	/* PC23 */ { 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
	/* PC19 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* RxClk (CLK13)   */
	/* PC18 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* TxClk (CLK14)   */
	/* PC17 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* RxClk (CLK15)   */
	/* PC16 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* TxClk (CLK16)   */
	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
	/* PC14 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 CD#	     */
	/* PC13 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CTS#	     */
	/* PC12 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CD#	     */
	/* PC11 */ { 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
	/* PC10 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC3 CD#	     */
	/* PC9	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC9	     */
	/* PC8	*/ { 1,		 1,   1,   0,	0,   0 }, /* SCC3 CTS#	     */
	/* PC7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
	/* PC6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
	/* PC5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
	/* PC4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
	/* PC3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
	/* PC2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
	/* PC1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
	/* PC0	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
    },

    /* Port D */
    {	/*	     conf      ppar psor pdir podr pdat */
	/* PD31 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 RXD	     */
	/* PD30 */ { 1,		 1,   1,   1,	0,   1 }, /* SCC1 TXD	     */
	/* PD29 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC1 RTS#	     */
	/* PD28 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 RXD	     */
	/* PD27 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC2 TXD	     */
	/* PD26 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC2 RTS#	     */
	/* PD25 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC3 RXD	     */
	/* PD24 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC3 TXD	     */
	/* PD23 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC3 RTS#	     */
	/* PD22 */ { 0,		 0,   0,   0,	0,   1 }, /* PD22	     */
	/* PD21 */ { 0,		 0,   0,   0,	0,   1 }, /* PD21	     */
	/* PD20 */ { 0,		 0,   0,   0,	0,   1 }, /* PD20	     */
	/* PD19 */ { 0,		 0,   0,   0,	0,   1 }, /* PD19	     */
	/* PD18 */ { 0,		 0,   0,   0,	0,   1 }, /* PD18	     */
	/* PD17 */ { 0,		 0,   0,   0,	0,   1 }, /* PD17	     */
	/* PD16 */ { 0,		 0,   0,   0,	0,   1 }, /* PD16	     */
	/* PD15 */ { 1,		 1,   1,   0,	1,   1 }, /* I2C SDA	     */
	/* PD14 */ { 1,		 1,   1,   0,	1,   1 }, /* I2C SCL	     */
	/* PD13 */ { 0,		 0,   0,   0,	0,   1 }, /* PD13	     */
	/* PD12 */ { 0,		 0,   0,   0,	0,   1 }, /* PD12	     */
	/* PD11 */ { 0,		 0,   0,   0,	0,   1 }, /* PD11	     */
	/* PD10 */ { 0,		 0,   0,   0,	0,   1 }, /* PD10	     */
	/* PD9	*/ { 1,		 1,   0,   1,	0,   1 }, /* SMC1 TxD	     */
	/* PD8	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC1 RxD	     */
	/* PD7	*/ { 1,		 1,   0,   0,	0,   1 }, /* SMC1 SMSYN      */
	/* PD6	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD6	     */
	/* PD5	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD5	     */
	/* PD4	*/ { 0,		 0,   0,   0,	0,   1 }, /* PD4	     */
	/* PD3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PD2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PD1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PD0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
    }
};

#ifdef CONFIG_PCI
typedef struct pci_ic_s {
	unsigned long pci_int_stat;
	unsigned long pci_int_mask;
}pci_ic_t;
#endif

int board_early_init_f (void)
{
	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;

	bcsr[4] |= 0x30; /* Turn the LEDs off */

#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
	bcsr[6] |= 0x10;
#endif
#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
	bcsr[7] |= 0x10;
#endif

#if CONFIG_SYS_FCC3
	bcsr[8] |= 0xC0;
#endif /* CONFIG_SYS_FCC3 */
#if CONFIG_SYS_FCC2
	bcsr[8] |= 0x30;
#endif /* CONFIG_SYS_FCC2 */

	return 0;
}

phys_size_t initdram(int board_type)
{
	/* Size in MB of SDRAM populated on board*/
	long int msize = 256;

#ifndef CONFIG_SYS_RAMBOOT
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	uint psdmr = CONFIG_SYS_PSDMR;
	int i;

	unsigned char	*ramptr1 = (unsigned char *)0x00000110;
	__maybe_unused unsigned char	ramtmp;

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

udelay(400);

	/* Initialise 60x bus SDRAM */
	memctl->memc_psrt = CONFIG_SYS_PSRT;
	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
	memctl->memc_psdmr = psdmr;

udelay(400);

	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
	ramtmp = *ramptr1;
	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
	for (i = 0; i < 8; i++) {
		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
	}
	ramtmp = *ramptr1;
	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
	*ramptr1  = 0xFF;
	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
#endif /* !CONFIG_SYS_RAMBOOT */

	/* Return total 60x bus SDRAM size */
	return msize * 1024 * 1024;
}

int checkboard(void)
{
	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;

	puts("Board: ");
	switch (bcsr[0]) {
	case 0x0A:
		printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
		break;
	default:
		printf("unknown: ID=%02X\n", bcsr[0]);
	}

	return 0;
}

#ifdef CONFIG_PCI
struct pci_controller hose;

extern void pci_mpc8250_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc8250_init(&hose);
}
#endif
Commit	Line	Data
7ce343e4 WD	1	/*
	2	* Copyright (C) 2006 Embedded Planet, LLC.
	3	*
	4	* Support for Embedded Planet EP82xxM boards.
	5	* Tested on EP82xxM (MPC8270).
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
7ce343e4 WD	8	*/
	9
	10	#include <common.h>
	11	#include <mpc8260.h>
	12	#include <ioports.h>
	13	#include <asm/m8260_pci.h>
	14	#ifdef CONFIG_PCI
	15	#include <pci.h>
	16	#endif
	17	#include <miiphy.h>
419abb6a	18	#include <linux/compiler.h>
7ce343e4 WD	19
	20	/*
	21	* I/O Port configuration table
	22	*
	23	* if conf is 1, then that port pin will be configured at boot time
	24	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	25	*/
	26
6d0f6bcf JCPV	27	#define CONFIG_SYS_FCC2 1
6d0f6bcf JCPV	28	#define CONFIG_SYS_FCC3 1
7ce343e4 WD	29
	30	const iop_conf_t iop_conf_tab[4][32] = {
	31
	32	/* Port A */
	33	{ /* conf ppar psor pdir podr pdat */
53677ef1 WD	34	/* PA31 / { 0, 0, 0, 0, 0, 1 }, / PA31 */
	35	/* PA30 / { 0, 0, 0, 0, 0, 1 }, / PA30 */
	36	/* PA29 / { 0, 0, 0, 0, 0, 1 }, / PA29 */
	37	/* PA28 / { 0, 0, 0, 0, 0, 1 }, / PA28 */
	38	/* PA27 / { 0, 0, 0, 0, 0, 1 }, / PA27 */
	39	/* PA26 / { 0, 0, 0, 0, 0, 1 }, / PA26 */
	40	/* PA25 / { 0, 0, 0, 0, 0, 1 }, / PA25 */
	41	/* PA24 / { 0, 0, 0, 0, 0, 1 }, / PA24 */
	42	/* PA23 / { 0, 0, 0, 0, 0, 1 }, / PA23 */
	43	/* PA22 / { 0, 0, 0, 0, 0, 0 }, / PA22 */
	44	/* PA21 / { 0, 0, 0, 0, 0, 1 }, / PA21 */
	45	/* PA20 / { 0, 0, 0, 0, 0, 1 }, / PA20 */
	46	/* PA19 / { 0, 0, 0, 0, 0, 1 }, / PA19 */
	47	/* PA18 / { 0, 0, 0, 0, 0, 1 }, / PA18 */
	48	/* PA17 / { 0, 0, 0, 0, 0, 1 }, / PA17 */
	49	/* PA16 / { 0, 0, 0, 0, 0, 1 }, / PA16 */
	50	/* PA15 / { 0, 0, 0, 0, 0, 1 }, / PA15 */
	51	/* PA14 / { 0, 0, 0, 0, 0, 1 }, / PA14 */
	52	/* PA13 / { 0, 0, 0, 0, 0, 1 }, / PA13 */
	53	/* PA12 / { 0, 0, 0, 0, 0, 1 }, / PA12 */
	54	/* PA11 / { 0, 0, 0, 0, 0, 1 }, / PA11 */
	55	/* PA10 / { 0, 0, 0, 0, 0, 1 }, / PA10 */
	56	/* PA9 / { 1, 1, 0, 1, 0, 1 }, / SMC2 TxD */
	57	/* PA8 / { 1, 1, 0, 0, 0, 1 }, / SMC2 RxD */
	58	/* PA7 / { 0, 0, 0, 0, 0, 1 }, / PA7 */
	59	/* PA6 / { 0, 0, 0, 0, 0, 1 }, / PA6 */
	60	/* PA5 / { 0, 0, 0, 0, 0, 1 }, / PA5 */
	61	/* PA4 / { 0, 0, 0, 0, 0, 1 }, / PA4 */
	62	/* PA3 / { 0, 0, 0, 0, 0, 1 }, / PA3 */
	63	/* PA2 / { 0, 0, 0, 0, 0, 1 }, / PA2 */
	64	/* PA1 / { 0, 0, 0, 0, 0, 1 }, / PA1 */
	65	/* PA0 / { 0, 0, 0, 0, 0, 1 } / PA0 */
7ce343e4 WD	66	},
	67
	68	/* Port B */
53677ef1	69	{ /* conf ppar psor pdir podr pdat */
6d0f6bcf JCPV	70	/* PB31 / { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	71	/* PB30 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	72	/* PB29 / { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	73	/* PB28 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	74	/* PB27 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	75	/* PB26 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	76	/* PB25 / { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	77	/* PB24 / { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	78	/* PB23 / { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	79	/* PB22 / { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	80	/* PB21 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	81	/* PB20 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	82	/* PB19 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	83	/* PB18 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
	84	/* PB17 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
	85	/* PB16 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
	86	/* PB15 / { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
	87	/* PB14 / { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
	88	/* PB13 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:COL */
	89	/* PB12 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:CRS */
	90	/* PB11 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	91	/* PB10 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	92	/* PB9 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:RXD */
	93	/* PB8 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / FCC3:RXD */
53677ef1	94	/* PB7 / { 0, 0, 0, 0, 0, 0 }, / PB7 */
6d0f6bcf JCPV	95	/* PB6 / { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, / FCC3:TXD */
	96	/* PB5 / { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, / FCC3:TXD */
	97	/* PB4 / { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, / FCC3:TXD */
53677ef1 WD	98	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	99	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	100	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	101	/* PB0 / { 0, 0, 0, 0, 0, 0 } / non-existent */
7ce343e4 WD	102	},
	103
	104	/* Port C */
53677ef1 WD	105	{ /* conf ppar psor pdir podr pdat */
	106	/* PC31 / { 0, 0, 0, 0, 0, 0 }, / PC31 */
	107	/* PC30 / { 0, 0, 0, 0, 0, 0 }, / PC30 */
	108	/* PC29 / { 1, 1, 1, 0, 0, 0 }, / SCC1 CTS# */
	109	/* PC28 / { 0, 0, 0, 0, 0, 0 }, / PC28 */
6d0f6bcf	110	/* PC27 / { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, / FCC3: TXD[0] */
53677ef1 WD	111	/* PC26 / { 0, 0, 0, 0, 0, 0 }, / PC26 */
	112	/* PC25 / { 0, 0, 0, 0, 0, 0 }, / PC25 */
	113	/* PC24 / { 0, 0, 0, 0, 0, 0 }, / PC24 */
	114	/* PC23 / { 0, 0, 0, 0, 0, 0 }, / PC23 */
	115	/* PC22 / { 0, 0, 0, 0, 0, 0 }, / PC22 */
	116	/* PC21 / { 0, 0, 0, 0, 0, 0 }, / PC21 */
	117	/* PC20 / { 0, 0, 0, 0, 0, 0 }, / PC20 */
6d0f6bcf JCPV	118	/* PC19 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / RxClk (CLK13) */
	119	/* PC18 / { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, / TxClk (CLK14) */
	120	/* PC17 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / RxClk (CLK15) */
	121	/* PC16 / { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, / TxClk (CLK16) */
53677ef1 WD	122	/* PC15 / { 0, 0, 0, 0, 0, 0 }, / PC15 */
	123	/* PC14 / { 1, 1, 0, 0, 0, 0 }, / SCC1 CD# */
	124	/* PC13 / { 1, 1, 0, 0, 0, 0 }, / SCC2 CTS# */
	125	/* PC12 / { 1, 1, 0, 0, 0, 0 }, / SCC2 CD# */
	126	/* PC11 / { 0, 0, 0, 0, 0, 0 }, / PC11 */
	127	/* PC10 / { 1, 1, 0, 0, 0, 0 }, / SCC3 CD# */
	128	/* PC9 / { 0, 0, 0, 0, 0, 0 }, / PC9 */
	129	/* PC8 / { 1, 1, 1, 0, 0, 0 }, / SCC3 CTS# */
	130	/* PC7 / { 0, 0, 0, 0, 0, 0 }, / PC7 */
	131	/* PC6 / { 0, 0, 0, 0, 0, 0 }, / PC6 */
	132	/* PC5 / { 0, 0, 0, 0, 0, 0 }, / PC5 */
	133	/* PC4 / { 0, 0, 0, 0, 0, 0 }, / PC4 */
	134	/* PC3 / { 0, 0, 0, 0, 0, 0 }, / PC3 */
	135	/* PC2 / { 0, 0, 0, 0, 0, 0 }, / PC2 */
	136	/* PC1 / { 0, 0, 0, 0, 0, 0 }, / PC1 */
	137	/* PC0 / { 0, 0, 0, 0, 0, 0 }, / PC0 */
7ce343e4 WD	138	},
	139
	140	/* Port D */
53677ef1 WD	141	{ /* conf ppar psor pdir podr pdat */
	142	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 RXD */
	143	/* PD30 / { 1, 1, 1, 1, 0, 1 }, / SCC1 TXD */
	144	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 RTS# */
	145	/* PD28 / { 1, 1, 0, 0, 0, 0 }, / SCC2 RXD */
	146	/* PD27 / { 1, 1, 0, 1, 0, 0 }, / SCC2 TXD */
	147	/* PD26 / { 1, 1, 0, 1, 0, 0 }, / SCC2 RTS# */
	148	/* PD25 / { 1, 1, 0, 0, 0, 0 }, / SCC3 RXD */
	149	/* PD24 / { 1, 1, 0, 1, 0, 0 }, / SCC3 TXD */
	150	/* PD23 / { 1, 1, 0, 1, 0, 0 }, / SCC3 RTS# */
	151	/* PD22 / { 0, 0, 0, 0, 0, 1 }, / PD22 */
	152	/* PD21 / { 0, 0, 0, 0, 0, 1 }, / PD21 */
	153	/* PD20 / { 0, 0, 0, 0, 0, 1 }, / PD20 */
	154	/* PD19 / { 0, 0, 0, 0, 0, 1 }, / PD19 */
	155	/* PD18 / { 0, 0, 0, 0, 0, 1 }, / PD18 */
	156	/* PD17 / { 0, 0, 0, 0, 0, 1 }, / PD17 */
	157	/* PD16 / { 0, 0, 0, 0, 0, 1 }, / PD16 */
	158	/* PD15 / { 1, 1, 1, 0, 1, 1 }, / I2C SDA */
	159	/* PD14 / { 1, 1, 1, 0, 1, 1 }, / I2C SCL */
	160	/* PD13 / { 0, 0, 0, 0, 0, 1 }, / PD13 */
	161	/* PD12 / { 0, 0, 0, 0, 0, 1 }, / PD12 */
	162	/* PD11 / { 0, 0, 0, 0, 0, 1 }, / PD11 */
	163	/* PD10 / { 0, 0, 0, 0, 0, 1 }, / PD10 */
	164	/* PD9 / { 1, 1, 0, 1, 0, 1 }, / SMC1 TxD */
	165	/* PD8 / { 1, 1, 0, 0, 0, 1 }, / SMC1 RxD */
	166	/* PD7 / { 1, 1, 0, 0, 0, 1 }, / SMC1 SMSYN */
	167	/* PD6 / { 0, 0, 0, 0, 0, 1 }, / PD6 */
	168	/* PD5 / { 0, 0, 0, 0, 0, 1 }, / PD5 */
	169	/* PD4 / { 0, 0, 0, 0, 0, 1 }, / PD4 */
	170	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	171	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	172	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	173	/* PD0 / { 0, 0, 0, 0, 0, 0 } / non-existent */
7ce343e4 WD	174	}
	175	};
	176
	177	#ifdef CONFIG_PCI
	178	typedef struct pci_ic_s {
	179	unsigned long pci_int_stat;
	180	unsigned long pci_int_mask;
	181	}pci_ic_t;
	182	#endif
	183
	184	int board_early_init_f (void)
	185	{
6d0f6bcf	186	vu_char bcsr = (vu_char )CONFIG_SYS_BCSR;
7ce343e4 WD	187
	188	bcsr[4] \|= 0x30; /* Turn the LEDs off */
	189
	190	#if defined(CONFIG_CONS_ON_SMC) \|\| defined(CONFIG_KGDB_ON_SMC)
	191	bcsr[6] \|= 0x10;
	192	#endif
	193	#if defined(CONFIG_CONS_ON_SCC) \|\| defined(CONFIG_KGDB_ON_SCC)
	194	bcsr[7] \|= 0x10;
	195	#endif
	196
6d0f6bcf	197	#if CONFIG_SYS_FCC3
7ce343e4	198	bcsr[8] \|= 0xC0;
6d0f6bcf JCPV	199	#endif /* CONFIG_SYS_FCC3 */
6d0f6bcf JCPV	200	#if CONFIG_SYS_FCC2
7ce343e4	201	bcsr[8] \|= 0x30;
6d0f6bcf	202	#endif /* CONFIG_SYS_FCC2 */
7ce343e4 WD	203
	204	return 0;
	205	}
	206
9973e3c6	207	phys_size_t initdram(int board_type)
7ce343e4 WD	208	{
	209	/* Size in MB of SDRAM populated on board*/
	210	long int msize = 256;
	211
6d0f6bcf JCPV	212	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	213	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
7ce343e4	214	volatile memctl8260_t *memctl = &immap->im_memctl;
6d0f6bcf	215	uint psdmr = CONFIG_SYS_PSDMR;
7ce343e4 WD	216	int i;
7ce343e4 WD	217
53677ef1	218	unsigned char ramptr1 = (unsigned char )0x00000110;
419abb6a	219	__maybe_unused unsigned char ramtmp;
7ce343e4	220
6d0f6bcf	221	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
7ce343e4 WD	222
	223	udelay(400);
	224
	225	/* Initialise 60x bus SDRAM */
6d0f6bcf JCPV	226	memctl->memc_psrt = CONFIG_SYS_PSRT;
	227	memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
	228	memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
7ce343e4 WD	229	memctl->memc_psdmr = psdmr;
	230
	231	udelay(400);
	232
	233	memctl->memc_psdmr = psdmr \| PSDMR_OP_PREA; /* Precharge all banks */
	234	ramtmp = *ramptr1;
	235	memctl->memc_psdmr = psdmr \| PSDMR_OP_CBRR; /* CBR refresh */
	236	for (i = 0; i < 8; i++) {
	237	memctl->memc_psdmr = psdmr \| PSDMR_OP_CBRR; /* CBR refresh */
	238	}
	239	ramtmp = *ramptr1;
	240	memctl->memc_psdmr = psdmr \| PSDMR_OP_MRW; /* Mode Register write */
	241	*ramptr1 = 0xFF;
	242	memctl->memc_psdmr = psdmr \| PSDMR_RFEN; /* Refresh enable */
6d0f6bcf	243	#endif /* !CONFIG_SYS_RAMBOOT */
7ce343e4 WD	244
	245	/* Return total 60x bus SDRAM size */
	246	return msize * 1024 * 1024;
	247	}
	248
	249	int checkboard(void)
	250	{
6d0f6bcf	251	vu_char bcsr = (vu_char )CONFIG_SYS_BCSR;
7ce343e4 WD	252
	253	puts("Board: ");
	254	switch (bcsr[0]) {
	255	case 0x0A:
	256	printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
	257	break;
	258	default:
	259	printf("unknown: ID=%02X\n", bcsr[0]);
	260	}
	261
	262	return 0;
	263	}
	264
	265	#ifdef CONFIG_PCI
	266	struct pci_controller hose;
	267
	268	extern void pci_mpc8250_init(struct pci_controller *);
	269
	270	void pci_init_board(void)
	271	{
	272	pci_mpc8250_init(&hose);
	273	}
	274	#endif