[people/ms/u-boot.git] / board / ep88x / ep88x.c

/*
 * Copyright (C) 2005 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * Support for Embedded Planet EP88x boards.
 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <common.h>
#include <mpc8xx.h>

/*
 * SDRAM uses two Micron chips.
 * Minimal CPU frequency is 40MHz.
 */
static uint sdram_table[] = {
	/* Single read	(offset 0x00 in UPM RAM) */
	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
	0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,

	/* Burst read	(offset 0x08 in UPM RAM) */
	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
	0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,

	/* Single write (offset 0x18 in UPM RAM) */
	0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
	0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,

	/* Burst write	(offset 0x20 in UPM RAM) */
	0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
	0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,

	/* Refresh	(offset 0x30 in UPM RAM) */
	0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
	0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
	0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,

	/* Exception	(offset 0x3C in UPM RAM) */
	0x0FEA8034, 0x1FB54034,	0xFFFFCC34, 0xFFFFCC05
};

int board_early_init_f (void)
{
	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;

	bcsr[0] |= 0x0C; /* Turn the LEDs off */
	bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
			    flash detection by CFI driver
			 */

#if defined(CONFIG_8xx_CONS_SMC1)
	bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
#endif
#if defined(CONFIG_8xx_CONS_SCC2)
	bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
#endif
#ifdef CONFIG_ETHER_ON_FEC1
	bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
#endif
#ifdef CONFIG_ETHER_ON_FEC2
	bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
#endif

	return 0;
}

phys_size_t initdram (int board_type)
{
	long int msize;
	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));

	/* Configure SDRAM refresh */
	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */

	memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */
	udelay(100);

	/* Run MRS pattern from location 0x36 */
	memctl->memc_mar = 0x88;
	memctl->memc_mcr = 0x80002236;
	udelay(100);

	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;

	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
	memctl->memc_or1  |= ~(msize - 1);

	return msize;
}

int checkboard( void )
{
	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;

	puts("Board: ");
	switch (bcsr[15]) {
	case 0xE7:
		puts("EP88xC 1.0");
		break;
	default:
		printf("unknown ID=%02X", bcsr[15]);
	}
	printf("  CPLD revision %d\n", bcsr[14]);

	return 0;
}
Commit	Line	Data
84c960ce WD	1	/*
	2	* Copyright (C) 2005 Arabella Software Ltd.
	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* Support for Embedded Planet EP88x boards.
	6	* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
84c960ce WD	9	*/
	10
	11	#include <common.h>
	12	#include <mpc8xx.h>
	13
	14	/*
	15	* SDRAM uses two Micron chips.
	16	* Minimal CPU frequency is 40MHz.
	17	*/
	18	static uint sdram_table[] = {
	19	/* Single read (offset 0x00 in UPM RAM) */
	20	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
	21	0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	22
	23	/* Burst read (offset 0x08 in UPM RAM) */
	24	0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
	25	0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
	26	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	27	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	28
	29	/* Single write (offset 0x18 in UPM RAM) */
	30	0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
	31	0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	32
	33	/* Burst write (offset 0x20 in UPM RAM) */
	34	0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
	35	0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
	36	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	37	0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
	38
	39	/* Refresh (offset 0x30 in UPM RAM) */
	40	0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
	41	0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
	42	0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
	43
	44	/* Exception (offset 0x3C in UPM RAM) */
	45	0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
	46	};
	47
	48	int board_early_init_f (void)
	49	{
6d0f6bcf	50	vu_char bcsr = (vu_char )CONFIG_SYS_BCSR;
84c960ce WD	51
	52	bcsr[0] \|= 0x0C; /* Turn the LEDs off */
	53	bcsr[2] \|= 0x08; /* Enable flash WE# line - necessary for
	54	flash detection by CFI driver
	55	*/
	56
	57	#if defined(CONFIG_8xx_CONS_SMC1)
	58	bcsr[6] \|= 0x10; /* Enables RS-232 transceiver */
	59	#endif
	60	#if defined(CONFIG_8xx_CONS_SCC2)
	61	bcsr[7] \|= 0x10; /* Enables RS-232 transceiver */
	62	#endif
	63	#ifdef CONFIG_ETHER_ON_FEC1
	64	bcsr[8] \|= 0xC0; /* Enable Ethernet 1 PHY */
	65	#endif
	66	#ifdef CONFIG_ETHER_ON_FEC2
	67	bcsr[8] \|= 0x30; /* Enable Ethernet 2 PHY */
	68	#endif
	69
	70	return 0;
	71	}
	72
9973e3c6	73	phys_size_t initdram (int board_type)
84c960ce WD	74	{
84c960ce WD	75	long int msize;
6d0f6bcf	76	volatile immap_t immap = (volatile immap_t )CONFIG_SYS_IMMR;
84c960ce WD	77	volatile memctl8xx_t *memctl = &immap->im_memctl;
	78
	79	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
	80
	81	/* Configure SDRAM refresh */
	82	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
	83
6d0f6bcf	84	memctl->memc_mamr = (65 << 24) \| CONFIG_SYS_MAMR; /* No refresh */
84c960ce WD	85	udelay(100);
	86
	87	/* Run MRS pattern from location 0x36 */
	88	memctl->memc_mar = 0x88;
	89	memctl->memc_mcr = 0x80002236;
	90	udelay(100);
	91
	92	memctl->memc_mamr \|= MAMR_PTAE; /* Enable refresh */
6d0f6bcf JCPV	93	memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) \| OR_CSNT_SAM;
6d0f6bcf JCPV	94	memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE \| BR_PS_32 \| BR_MS_UPMA \| BR_V;
84c960ce	95
6d0f6bcf	96	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
84c960ce WD	97	memctl->memc_or1 \|= ~(msize - 1);
	98
	99	return msize;
	100	}
	101
	102	int checkboard( void )
	103	{
6d0f6bcf	104	vu_char bcsr = (vu_char )CONFIG_SYS_BCSR;
84c960ce WD	105
	106	puts("Board: ");
	107	switch (bcsr[15]) {
	108	case 0xE7:
	109	puts("EP88xC 1.0");
	110	break;
	111	default:
	112	printf("unknown ID=%02X", bcsr[15]);
	113	}
	114	printf(" CPLD revision %d\n", bcsr[14]);
	115
	116	return 0;
	117	}