[people/ms/u-boot.git] / board / esd / apc405 / apc405.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);

/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
{
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);


#ifdef CONFIG_LCD_USED
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp[] =
{
#include CFG_LCD_LOGO_NAME
};

/*
 * include common lcd code (for esd boards)
 */
#include "../common/lcd.c"

#include "../common/"CFG_LCD_HEADER_NAME
#endif /* CONFIG_LCD_USED */


int board_early_init_f (void)
{
	/*
	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
	 */
	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
	out32(GPIO0_OR, 0);                  /* pull prg low            */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
#if 1 /* test-only */
	mtebc (epcr, 0xa8400000); /* ebc always driven */
#else
	mtebc (epcr, 0x28400000); /* ebc in high-z */
#endif

	return 0;
}


/* ------------------------------------------------------------------------- */

int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	volatile unsigned char *duart0_mcr =
		(unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr =
		(unsigned char *)((ulong)DUART1_BA + 4);
	volatile unsigned short *fuji_lcdbl_pwm =
		(unsigned short *)((ulong)0xf0100200 + 0xa0);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long cntrl0Reg;

	/*
	 * Setup GPIO pins (CS6+CS7 as GPIO)
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | 0x00300000);

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	/* restore gpio/cs settings */
	mtdcr(cntrl0, cntrl0Reg);

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

	/*
	 * Enable power on PS/2 interface (with reset)
	 */
	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
	for (i=0;i<100;i++)
		udelay(1000);
	udelay(1000);
	*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;

	/*
	 * Init lcd interface and display logo
	 */
	lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
		 regs_13806_640_480_16bpp,
		 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
		 logo_bmp, sizeof(logo_bmp));

	/*
	 * Enable microcontroller and setup backlight PWM controller
	 */
	*fpga_mode |= 0x001c;
	*fuji_lcdbl_pwm = 0x00ff;

	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	unsigned char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming APC405");
	} else {
		puts(str);
	}

	putc ('\n');

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_IDE_RESET

void ide_set_reset(int on)
{
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);

	/*
	 * Assert or deassert CompactFlash Reset Pin
	 */
	if (on) {		/* assert RESET */
		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
	} else {		/* release RESET */
		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
	}
}

#endif /* CONFIG_IDE_RESET */

/* ------------------------------------------------------------------------- */
Commit	Line	Data
1bc0f141 SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
	29	/* ------------------------------------------------------------------------- */
	30
	31	#if 0
	32	#define FPGA_DEBUG
	33	#endif
	34
	35	extern int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char argv[]);
	36	extern void lxt971_no_sleep(void);
	37
	38	/* fpga configuration data - gzip compressed and generated by bin2c */
	39	const unsigned char fpgadata[] =
	40	{
	41	#include "fpgadata.c"
	42	};
	43
	44	/*
	45	* include common fpga code (for esd boards)
	46	*/
	47	#include "../common/fpga.c"
	48
	49
	50	/* Prototypes */
	51	int gunzip(void , int, unsigned char , unsigned long *);
	52
	53
	54	#ifdef CONFIG_LCD_USED
	55	/* logo bitmap data - gzip compressed and generated by bin2c */
	56	unsigned char logo_bmp[] =
	57	{
	58	#include CFG_LCD_LOGO_NAME
	59	};
	60
	61	/*
	62	* include common lcd code (for esd boards)
	63	*/
	64	#include "../common/lcd.c"
65
66	#include "../common/"CFG_LCD_HEADER_NAME
67	#endif /* CONFIG_LCD_USED */
68
69
70	int board_early_init_f (void)
71	{
72	/*
73	* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
74	*/
75	out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
76	out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
77	out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
78	out32(GPIO0_OR, 0); /* pull prg low */
79
80	/*
81	* IRQ 0-15 405GP internally generated; active high; level sensitive
82	* IRQ 16 405GP internally generated; active low; level sensitive
83	* IRQ 17-24 RESERVED
84	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
85	* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
86	* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
87	* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
88	* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
89	* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
90	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
91	*/
92	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
93	mtdcr(uicer, 0x00000000); /* disable all ints */
94	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
95	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
96	mtdcr(uictr, 0x10000000); /* set int trigger levels */
97	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
98	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
99
100	/*
101	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
102	*/
103	#if 1 /* test-only */
104	mtebc (epcr, 0xa8400000); /* ebc always driven */
105	#else
106	mtebc (epcr, 0x28400000); /* ebc in high-z */
107	#endif
108
109	return 0;
110	}
111
112
113	/* ------------------------------------------------------------------------- */
114
115	int misc_init_f (void)
116	{
117	return 0; /* dummy implementation */
118	}
119
120
121	int misc_init_r (void)
122	{
123	volatile unsigned short *fpga_mode =
124	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
125	volatile unsigned char *duart0_mcr =
126	(unsigned char *)((ulong)DUART0_BA + 4);
127	volatile unsigned char *duart1_mcr =
128	(unsigned char *)((ulong)DUART1_BA + 4);
129	volatile unsigned short *fuji_lcdbl_pwm =
130	(unsigned short *)((ulong)0xf0100200 + 0xa0);
131	unsigned char *dst;
132	ulong len = sizeof(fpgadata);
133	int status;
134	int index;
135	int i;
136	unsigned long cntrl0Reg;
137
138	/*
139	* Setup GPIO pins (CS6+CS7 as GPIO)
140	*/
141	cntrl0Reg = mfdcr(cntrl0);
142	mtdcr(cntrl0, cntrl0Reg \| 0x00300000);
143
144	dst = malloc(CFG_FPGA_MAX_SIZE);
145	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
146	printf ("GUNZIP ERROR - must RESET board to recover\n");
147	do_reset (NULL, 0, 0, NULL);
148	}
149
150	status = fpga_boot(dst, len);
151	if (status != 0) {
152	printf("\nFPGA: Booting failed ");
153	switch (status) {
154	case ERROR_FPGA_PRG_INIT_LOW:
155	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
156	break;
157	case ERROR_FPGA_PRG_INIT_HIGH:
158	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
159	break;
160	case ERROR_FPGA_PRG_DONE:
161	printf("(Timeout: DONE not high after programming FPGA)\n ");
162	break;
163	}
164
165	/* display infos on fpgaimage */
166	index = 15;
167	for (i=0; i<4; i++) {
168	len = dst[index];
169	printf("FPGA: %s\n", &(dst[index+1]));
170	index += len+3;
171	}
172	putc ('\n');
173	/* delayed reboot */
174	for (i=20; i>0; i--) {
175	printf("Rebooting in %2d seconds \r",i);
176	for (index=0;index<1000;index++)
177	udelay(1000);
178	}
179	putc ('\n');
180	do_reset(NULL, 0, 0, NULL);
181	}
182
183	/* restore gpio/cs settings */
184	mtdcr(cntrl0, cntrl0Reg);
185
186	puts("FPGA: ");
187
188	/* display infos on fpgaimage */
189	index = 15;
190	for (i=0; i<4; i++) {
191	len = dst[index];
192	printf("%s ", &(dst[index+1]));
193	index += len+3;
194	}
195	putc ('\n');
196
197	free(dst);
198
199	/*
200	* Reset FPGA via FPGA_DATA pin
201	*/
202	SET_FPGA(FPGA_PRG \| FPGA_CLK);
203	udelay(1000); /* wait 1ms */
204	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
205	udelay(1000); /* wait 1ms */
206
207	/*
208	* Enable power on PS/2 interface (with reset)
209	*/
210	*fpga_mode \|= CFG_FPGA_CTRL_PS2_RESET;
211	for (i=0;i<100;i++)
212	udelay(1000);
213	udelay(1000);
214	*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
215
216	/*
217	* Enable interrupts in exar duart mcr[3]
218	*/
219	*duart0_mcr = 0x08;
220	*duart1_mcr = 0x08;
221
222	/*
223	* Init lcd interface and display logo
224	*/
225	lcd_init((uchar )CFG_LCD_BIG_REG, (uchar )CFG_LCD_BIG_MEM,
226	regs_13806_640_480_16bpp,
227	sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
228	logo_bmp, sizeof(logo_bmp));
229
230	/*
231	* Enable microcontroller and setup backlight PWM controller
232	*/
233	*fpga_mode \|= 0x001c;
234	*fuji_lcdbl_pwm = 0x00ff;
235
236	return (0);
237	}
238
239
240	/*
241	* Check Board Identity:
242	*/
243
244	int checkboard (void)
245	{
246	unsigned char str[64];
247	int i = getenv_r ("serial#", str, sizeof(str));
248
249	puts ("Board: ");
250
251	if (i == -1) {
252	puts ("### No HW ID - assuming APC405");
253	} else {
254	puts(str);
255	}
256
257	putc ('\n');
258
259	/*
260	* Disable sleep mode in LXT971
261	*/
262	lxt971_no_sleep();
263
264	return 0;
265	}
266
267	/* ------------------------------------------------------------------------- */
268
269	long int initdram (int board_type)
270	{
271	unsigned long val;
272
273	mtdcr(memcfga, mem_mb0cf);
274	val = mfdcr(memcfgd);
275
276	#if 0
277	printf("\nmb0cf=%x\n", val); /* test-only */
278	printf("strap=%x\n", mfdcr(strap)); /* test-only */
279	#endif
280
281	return (410241024 << ((val & 0x000e0000) >> 17));
282	}
283
284	/* ------------------------------------------------------------------------- */
285
286	int testdram (void)
287	{
288	/* TODO: XXX XXX XXX */
289	printf ("test: 16 MB - ok\n");
290
291	return (0);
292	}
293
294	/* ------------------------------------------------------------------------- */
295
296	#ifdef CONFIG_IDE_RESET
297
298	void ide_set_reset(int on)
299	{
300	volatile unsigned short *fpga_mode =
301	(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
302
303	/*
304	* Assert or deassert CompactFlash Reset Pin
305	*/
306	if (on) { /* assert RESET */
307	*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
308	} else { /* release RESET */
309	*fpga_mode \|= CFG_FPGA_CTRL_CF_RESET;
310	}
311	}
312
313	#endif /* CONFIG_IDE_RESET */
314
315	/* ------------------------------------------------------------------------- */