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1bc0f141 | 1 | /* |
0b987251 MF |
2 | * (C) Copyright 2005-2008 |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
1bc0f141 SR |
5 | * (C) Copyright 2001-2003 |
6 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <asm/processor.h> | |
0b987251 | 29 | #include <asm/io.h> |
1bc0f141 SR |
30 | #include <command.h> |
31 | #include <malloc.h> | |
0b987251 MF |
32 | #include <flash.h> |
33 | #include <asm/4xx_pci.h> | |
34 | #include <pci.h> | |
1bc0f141 | 35 | |
d87080b7 | 36 | DECLARE_GLOBAL_DATA_PTR; |
1bc0f141 | 37 | |
0b987251 | 38 | #undef FPGA_DEBUG |
1bc0f141 SR |
39 | |
40 | extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); | |
41 | extern void lxt971_no_sleep(void); | |
0b987251 MF |
42 | extern ulong flash_get_size (ulong base, int banknum); |
43 | ||
44 | int flash_banks = CFG_MAX_FLASH_BANKS_DETECT; | |
1bc0f141 SR |
45 | |
46 | /* fpga configuration data - gzip compressed and generated by bin2c */ | |
47 | const unsigned char fpgadata[] = | |
48 | { | |
49 | #include "fpgadata.c" | |
50 | }; | |
51 | ||
52 | /* | |
53 | * include common fpga code (for esd boards) | |
54 | */ | |
55 | #include "../common/fpga.c" | |
56 | ||
1bc0f141 SR |
57 | /* Prototypes */ |
58 | int gunzip(void *, int, unsigned char *, unsigned long *); | |
59 | ||
1bc0f141 SR |
60 | #ifdef CONFIG_LCD_USED |
61 | /* logo bitmap data - gzip compressed and generated by bin2c */ | |
62 | unsigned char logo_bmp[] = | |
63 | { | |
0b987251 | 64 | #include "logo_640_480_24bpp.c" |
1bc0f141 SR |
65 | }; |
66 | ||
67 | /* | |
68 | * include common lcd code (for esd boards) | |
69 | */ | |
70 | #include "../common/lcd.c" | |
0b987251 MF |
71 | #include "../common/s1d13505_640_480_16bpp.h" |
72 | #include "../common/s1d13806_640_480_16bpp.h" | |
1bc0f141 SR |
73 | #endif /* CONFIG_LCD_USED */ |
74 | ||
0b987251 MF |
75 | /* |
76 | * include common auto-update code (for esd boards) | |
77 | */ | |
78 | #include "../common/auto_update.h" | |
79 | ||
80 | au_image_t au_image[] = { | |
81 | {"preinst.img", 0, -1, AU_SCRIPT}, | |
82 | {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT}, | |
83 | {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT}, | |
84 | {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT}, | |
85 | {"work.img", 0xfe500000, 0x01400000, AU_NOR}, | |
86 | {"data.img", 0xff900000, 0x00580000, AU_NOR}, | |
87 | {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT}, | |
88 | {"postinst.img", 0, 0, AU_SCRIPT}, | |
89 | }; | |
90 | ||
91 | int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); | |
1bc0f141 | 92 | |
04e93ec9 SR |
93 | int board_revision(void) |
94 | { | |
95 | unsigned long cntrl0Reg; | |
0b987251 | 96 | volatile unsigned long value; |
04e93ec9 SR |
97 | |
98 | /* | |
99 | * Get version of APC405 board from GPIO's | |
100 | */ | |
101 | ||
0b987251 | 102 | /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ |
04e93ec9 | 103 | cntrl0Reg = mfdcr(cntrl0); |
0b987251 MF |
104 | mtdcr(cntrl0, cntrl0Reg | 0x03800000); |
105 | out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); | |
106 | out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); | |
107 | ||
108 | /* wait some time before reading input */ | |
109 | udelay(1000); | |
04e93ec9 | 110 | |
0b987251 MF |
111 | /* get config bits */ |
112 | value = in_be32((void*)GPIO0_IR) & 0x001c0000; | |
04e93ec9 SR |
113 | /* |
114 | * Restore GPIO settings | |
115 | */ | |
116 | mtdcr(cntrl0, cntrl0Reg); | |
117 | ||
118 | switch (value) { | |
0b987251 MF |
119 | case 0x001c0000: |
120 | /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */ | |
04e93ec9 | 121 | return 2; |
0b987251 MF |
122 | case 0x000c0000: |
123 | /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */ | |
04e93ec9 | 124 | return 3; |
0b987251 MF |
125 | case 0x00180000: |
126 | /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */ | |
127 | return 6; | |
128 | case 0x00140000: | |
129 | /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */ | |
130 | return 8; | |
04e93ec9 SR |
131 | default: |
132 | /* should not be reached! */ | |
133 | return 0; | |
134 | } | |
135 | } | |
136 | ||
1bc0f141 SR |
137 | int board_early_init_f (void) |
138 | { | |
139 | /* | |
0b987251 | 140 | * First pull fpga-prg pin low, to disable fpga logic |
1bc0f141 | 141 | */ |
0b987251 MF |
142 | out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ |
143 | out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ | |
144 | out_be32((void*)GPIO0_OR, 0); /* pull prg low */ | |
1bc0f141 SR |
145 | |
146 | /* | |
147 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
148 | * IRQ 16 405GP internally generated; active low; level sensitive | |
149 | * IRQ 17-24 RESERVED | |
150 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
151 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive | |
152 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive | |
153 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive | |
154 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive | |
155 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive | |
156 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
157 | */ | |
158 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
159 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
160 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
161 | mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ | |
162 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ | |
0b987251 | 163 | mtdcr(uicvcr, 0x00000001); /* set vect base=0 */ |
1bc0f141 SR |
164 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
165 | ||
166 | /* | |
0b987251 MF |
167 | * EBC Configuration Register: set ready timeout to 512 ebc-clks |
168 | */ | |
169 | mtebc(epcr, 0xa8400000); /* ebc always driven */ | |
170 | ||
171 | /* | |
172 | * New boards have a single 32MB flash connected to CS0 | |
173 | * instead of two 16MB flashes on CS0+1. | |
1bc0f141 | 174 | */ |
0b987251 MF |
175 | if (board_revision() >= 8) { |
176 | /* disable CS1 */ | |
177 | mtebc(pb1ap, 0); | |
178 | mtebc(pb1cr, 0); | |
179 | ||
180 | /* resize CS0 to 32MB */ | |
181 | mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8); | |
182 | mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8); | |
183 | } | |
1bc0f141 SR |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
0b987251 | 188 | int board_early_init_r(void) |
1bc0f141 | 189 | { |
0b987251 MF |
190 | if (gd->board_type >= 8) |
191 | flash_banks = 1; | |
192 | ||
193 | return 0; | |
1bc0f141 SR |
194 | } |
195 | ||
0b987251 MF |
196 | #define FUJI_BASE 0xf0100200 |
197 | #define LCDBL_PWM 0xa0 | |
198 | #define LCDBL_PWMMIN 0xa4 | |
199 | #define LCDBL_PWMMAX 0xa8 | |
1bc0f141 | 200 | |
0b987251 | 201 | int misc_init_r(void) |
1bc0f141 | 202 | { |
0b987251 MF |
203 | u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); |
204 | u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); | |
205 | u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); | |
206 | u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); | |
1bc0f141 SR |
207 | unsigned char *dst; |
208 | ulong len = sizeof(fpgadata); | |
209 | int status; | |
210 | int index; | |
211 | int i; | |
212 | unsigned long cntrl0Reg; | |
0b987251 MF |
213 | char *str; |
214 | uchar *logo_addr; | |
215 | ulong logo_size; | |
216 | ushort minb, maxb; | |
217 | int result; | |
1bc0f141 SR |
218 | |
219 | /* | |
220 | * Setup GPIO pins (CS6+CS7 as GPIO) | |
221 | */ | |
222 | cntrl0Reg = mfdcr(cntrl0); | |
223 | mtdcr(cntrl0, cntrl0Reg | 0x00300000); | |
224 | ||
225 | dst = malloc(CFG_FPGA_MAX_SIZE); | |
0b987251 MF |
226 | if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { |
227 | printf("GUNZIP ERROR - must RESET board to recover\n"); | |
228 | do_reset(NULL, 0, 0, NULL); | |
1bc0f141 SR |
229 | } |
230 | ||
231 | status = fpga_boot(dst, len); | |
232 | if (status != 0) { | |
233 | printf("\nFPGA: Booting failed "); | |
234 | switch (status) { | |
235 | case ERROR_FPGA_PRG_INIT_LOW: | |
0b987251 MF |
236 | printf("(Timeout: " |
237 | "INIT not low after asserting PROGRAM*)\n "); | |
1bc0f141 SR |
238 | break; |
239 | case ERROR_FPGA_PRG_INIT_HIGH: | |
0b987251 MF |
240 | printf("(Timeout: " |
241 | "INIT not high after deasserting PROGRAM*)\n "); | |
1bc0f141 SR |
242 | break; |
243 | case ERROR_FPGA_PRG_DONE: | |
0b987251 MF |
244 | printf("(Timeout: " |
245 | "DONE not high after programming FPGA)\n "); | |
1bc0f141 SR |
246 | break; |
247 | } | |
248 | ||
249 | /* display infos on fpgaimage */ | |
250 | index = 15; | |
0b987251 | 251 | for (i = 0; i < 4; i++) { |
1bc0f141 SR |
252 | len = dst[index]; |
253 | printf("FPGA: %s\n", &(dst[index+1])); | |
0b987251 | 254 | index += len + 3; |
1bc0f141 | 255 | } |
0b987251 | 256 | putc('\n'); |
1bc0f141 | 257 | /* delayed reboot */ |
0b987251 | 258 | for (i = 20; i > 0; i--) { |
1bc0f141 | 259 | printf("Rebooting in %2d seconds \r",i); |
0b987251 | 260 | for (index = 0; index < 1000; index++) |
1bc0f141 SR |
261 | udelay(1000); |
262 | } | |
0b987251 | 263 | putc('\n'); |
1bc0f141 SR |
264 | do_reset(NULL, 0, 0, NULL); |
265 | } | |
266 | ||
267 | /* restore gpio/cs settings */ | |
268 | mtdcr(cntrl0, cntrl0Reg); | |
269 | ||
270 | puts("FPGA: "); | |
271 | ||
272 | /* display infos on fpgaimage */ | |
273 | index = 15; | |
0b987251 | 274 | for (i = 0; i < 4; i++) { |
1bc0f141 | 275 | len = dst[index]; |
0b987251 MF |
276 | printf("%s ", &(dst[index + 1])); |
277 | index += len + 3; | |
1bc0f141 | 278 | } |
0b987251 | 279 | putc('\n'); |
1bc0f141 SR |
280 | |
281 | free(dst); | |
282 | ||
283 | /* | |
284 | * Reset FPGA via FPGA_DATA pin | |
285 | */ | |
286 | SET_FPGA(FPGA_PRG | FPGA_CLK); | |
287 | udelay(1000); /* wait 1ms */ | |
288 | SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); | |
289 | udelay(1000); /* wait 1ms */ | |
290 | ||
04e93ec9 SR |
291 | /* |
292 | * Write board revision in FPGA | |
293 | */ | |
0b987251 MF |
294 | out_be16(fpga_ctrl2, |
295 | (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f)); | |
04e93ec9 | 296 | |
1bc0f141 SR |
297 | /* |
298 | * Enable power on PS/2 interface (with reset) | |
299 | */ | |
0b987251 | 300 | out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET); |
1bc0f141 SR |
301 | for (i=0;i<100;i++) |
302 | udelay(1000); | |
303 | udelay(1000); | |
0b987251 | 304 | out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET); |
1bc0f141 SR |
305 | |
306 | /* | |
307 | * Enable interrupts in exar duart mcr[3] | |
308 | */ | |
0b987251 MF |
309 | out_8(duart0_mcr, 0x08); |
310 | out_8(duart1_mcr, 0x08); | |
1bc0f141 SR |
311 | |
312 | /* | |
313 | * Init lcd interface and display logo | |
314 | */ | |
0b987251 MF |
315 | str = getenv("splashimage"); |
316 | if (str) { | |
317 | logo_addr = (uchar *)simple_strtoul(str, NULL, 16); | |
318 | logo_size = CFG_VIDEO_LOGO_MAX_SIZE; | |
319 | } else { | |
320 | logo_addr = logo_bmp; | |
321 | logo_size = sizeof(logo_bmp); | |
322 | } | |
323 | ||
324 | if (gd->board_type >= 6) { | |
325 | result = lcd_init((uchar *)CFG_LCD_BIG_REG, | |
326 | (uchar *)CFG_LCD_BIG_MEM, | |
327 | regs_13505_640_480_16bpp, | |
328 | sizeof(regs_13505_640_480_16bpp) / | |
329 | sizeof(regs_13505_640_480_16bpp[0]), | |
330 | logo_addr, logo_size); | |
331 | if (result && str) { | |
332 | /* retry with internal image */ | |
333 | logo_addr = logo_bmp; | |
334 | logo_size = sizeof(logo_bmp); | |
335 | lcd_init((uchar *)CFG_LCD_BIG_REG, | |
336 | (uchar *)CFG_LCD_BIG_MEM, | |
337 | regs_13505_640_480_16bpp, | |
338 | sizeof(regs_13505_640_480_16bpp) / | |
339 | sizeof(regs_13505_640_480_16bpp[0]), | |
340 | logo_addr, logo_size); | |
341 | } | |
342 | } else { | |
343 | result = lcd_init((uchar *)CFG_LCD_BIG_REG, | |
344 | (uchar *)CFG_LCD_BIG_MEM, | |
345 | regs_13806_640_480_16bpp, | |
346 | sizeof(regs_13806_640_480_16bpp) / | |
347 | sizeof(regs_13806_640_480_16bpp[0]), | |
348 | logo_addr, logo_size); | |
349 | if (result && str) { | |
350 | /* retry with internal image */ | |
351 | logo_addr = logo_bmp; | |
352 | logo_size = sizeof(logo_bmp); | |
353 | lcd_init((uchar *)CFG_LCD_BIG_REG, | |
354 | (uchar *)CFG_LCD_BIG_MEM, | |
355 | regs_13806_640_480_16bpp, | |
356 | sizeof(regs_13806_640_480_16bpp) / | |
357 | sizeof(regs_13806_640_480_16bpp[0]), | |
358 | logo_addr, logo_size); | |
359 | } | |
360 | } | |
1bc0f141 SR |
361 | |
362 | /* | |
04e93ec9 | 363 | * Reset microcontroller and setup backlight PWM controller |
1bc0f141 | 364 | */ |
0b987251 | 365 | out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014); |
04e93ec9 SR |
366 | for (i=0;i<10;i++) |
367 | udelay(1000); | |
0b987251 MF |
368 | out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c); |
369 | ||
370 | minb = 0; | |
371 | maxb = 0xff; | |
372 | str = getenv("lcdbl"); | |
373 | if (str) { | |
374 | minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff; | |
375 | if (str && (*str=',')) { | |
376 | str++; | |
377 | maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff; | |
378 | } else | |
379 | minb = 0; | |
380 | ||
381 | out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb); | |
382 | out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb); | |
383 | ||
384 | printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb); | |
385 | } | |
386 | out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff); | |
387 | ||
8e048c43 MF |
388 | /* |
389 | * fix environment for field updated units | |
390 | */ | |
391 | if (getenv("altbootcmd") == NULL) { | |
0b987251 MF |
392 | setenv("usb_load", CFG_USB_LOAD_COMMAND); |
393 | setenv("usbargs", CFG_USB_ARGS); | |
394 | setenv("bootcmd", CONFIG_BOOTCOMMAND); | |
395 | setenv("usb_self", CFG_USB_SELF_COMMAND); | |
8e048c43 MF |
396 | setenv("bootlimit", CFG_BOOTLIMIT); |
397 | setenv("altbootcmd", CFG_ALT_BOOTCOMMAND); | |
0b987251 MF |
398 | saveenv(); |
399 | } | |
1bc0f141 SR |
400 | |
401 | return (0); | |
402 | } | |
403 | ||
1bc0f141 SR |
404 | /* |
405 | * Check Board Identity: | |
406 | */ | |
1bc0f141 SR |
407 | int checkboard (void) |
408 | { | |
0b987251 | 409 | char str[64]; |
1bc0f141 SR |
410 | int i = getenv_r ("serial#", str, sizeof(str)); |
411 | ||
412 | puts ("Board: "); | |
413 | ||
414 | if (i == -1) { | |
415 | puts ("### No HW ID - assuming APC405"); | |
416 | } else { | |
417 | puts(str); | |
418 | } | |
419 | ||
04e93ec9 | 420 | gd->board_type = board_revision(); |
0b987251 | 421 | printf(", Rev. 1.%ld\n", gd->board_type); |
1bc0f141 SR |
422 | |
423 | return 0; | |
424 | } | |
425 | ||
9973e3c6 | 426 | phys_size_t initdram (int board_type) |
1bc0f141 SR |
427 | { |
428 | unsigned long val; | |
429 | ||
430 | mtdcr(memcfga, mem_mb0cf); | |
431 | val = mfdcr(memcfgd); | |
432 | ||
1bc0f141 SR |
433 | return (4*1024*1024 << ((val & 0x000e0000) >> 17)); |
434 | } | |
435 | ||
0b987251 MF |
436 | #ifdef CONFIG_IDE_RESET |
437 | void ide_set_reset(int on) | |
1bc0f141 | 438 | { |
0b987251 | 439 | u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); |
1bc0f141 | 440 | |
0b987251 MF |
441 | /* |
442 | * Assert or deassert CompactFlash Reset Pin | |
443 | */ | |
444 | if (on) { | |
445 | out_be16(fpga_mode, | |
446 | in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET); | |
447 | } else { | |
448 | out_be16(fpga_mode, | |
449 | in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET); | |
450 | } | |
1bc0f141 | 451 | } |
0b987251 | 452 | #endif /* CONFIG_IDE_RESET */ |
1bc0f141 | 453 | |
0b987251 MF |
454 | void reset_phy(void) |
455 | { | |
456 | /* | |
457 | * Disable sleep mode in LXT971 | |
458 | */ | |
459 | lxt971_no_sleep(); | |
460 | } | |
1bc0f141 | 461 | |
0b987251 MF |
462 | #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) |
463 | int usb_board_init(void) | |
464 | { | |
465 | return 0; | |
466 | } | |
1bc0f141 | 467 | |
0b987251 | 468 | int usb_board_stop(void) |
1bc0f141 | 469 | { |
0b987251 MF |
470 | unsigned short tmp; |
471 | int i; | |
1bc0f141 SR |
472 | |
473 | /* | |
0b987251 MF |
474 | * reset PCI bus |
475 | * This is required to make some very old Linux OHCI driver | |
476 | * work after U-Boot has used the OHCI controller. | |
1bc0f141 | 477 | */ |
0b987251 MF |
478 | pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp); |
479 | pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000)); | |
1bc0f141 | 480 | |
0b987251 MF |
481 | for (i = 0; i < 100; i++) |
482 | udelay(1000); | |
1bc0f141 | 483 | |
0b987251 MF |
484 | pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp); |
485 | return 0; | |
486 | } | |
487 | ||
488 | int usb_board_init_fail(void) | |
489 | { | |
490 | usb_board_stop(); | |
491 | return 0; | |
492 | } | |
493 | #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ |