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c93f7096 SR |
1 | /* |
2 | * (C) Copyright 2001-2003 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
bd84ee4c | 26 | #include <asm/io.h> |
c93f7096 | 27 | #include <command.h> |
c93f7096 SR |
28 | #include <malloc.h> |
29 | ||
30 | /* ------------------------------------------------------------------------- */ | |
31 | ||
32 | #if 0 | |
33 | #define FPGA_DEBUG | |
34 | #endif | |
35 | ||
8bde7f77 | 36 | extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
bd84ee4c | 37 | extern void lxt971_no_sleep(void); |
8bde7f77 | 38 | |
c93f7096 SR |
39 | /* fpga configuration data - gzip compressed and generated by bin2c */ |
40 | const unsigned char fpgadata[] = | |
41 | { | |
42 | #include "fpgadata.c" | |
43 | }; | |
44 | ||
45 | /* | |
46 | * include common fpga code (for esd boards) | |
47 | */ | |
48 | #include "../common/fpga.c" | |
49 | ||
50 | ||
51 | /* Prototypes */ | |
eedcd078 | 52 | int gunzip(void *, int, unsigned char *, unsigned long *); |
c93f7096 SR |
53 | |
54 | ||
c837dcb1 | 55 | int board_early_init_f (void) |
c93f7096 SR |
56 | { |
57 | /* | |
58 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
59 | * IRQ 16 405GP internally generated; active low; level sensitive | |
60 | * IRQ 17-24 RESERVED | |
61 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
62 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive | |
63 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive | |
64 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive | |
65 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive | |
66 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive | |
67 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
68 | */ | |
69 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
70 | mtdcr(uicer, 0x00000000); /* disable all ints */ | |
71 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ | |
5b8b6525 | 72 | mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ |
c93f7096 SR |
73 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
74 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
75 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ | |
76 | ||
77 | /* | |
78 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us | |
79 | */ | |
d1c3b275 | 80 | mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
c93f7096 SR |
81 | |
82 | return 0; | |
83 | } | |
84 | ||
c93f7096 SR |
85 | int misc_init_r (void) |
86 | { | |
c93f7096 SR |
87 | unsigned char *dst; |
88 | ulong len = sizeof(fpgadata); | |
89 | int status; | |
90 | int index; | |
91 | int i; | |
92 | ||
6d0f6bcf JCPV |
93 | dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
94 | if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { | |
c93f7096 SR |
95 | printf ("GUNZIP ERROR - must RESET board to recover\n"); |
96 | do_reset (NULL, 0, 0, NULL); | |
97 | } | |
98 | ||
99 | status = fpga_boot(dst, len); | |
100 | if (status != 0) { | |
101 | printf("\nFPGA: Booting failed "); | |
102 | switch (status) { | |
103 | case ERROR_FPGA_PRG_INIT_LOW: | |
104 | printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); | |
105 | break; | |
106 | case ERROR_FPGA_PRG_INIT_HIGH: | |
107 | printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); | |
108 | break; | |
109 | case ERROR_FPGA_PRG_DONE: | |
110 | printf("(Timeout: DONE not high after programming FPGA)\n "); | |
111 | break; | |
112 | } | |
113 | ||
114 | /* display infos on fpgaimage */ | |
115 | index = 15; | |
116 | for (i=0; i<4; i++) { | |
117 | len = dst[index]; | |
118 | printf("FPGA: %s\n", &(dst[index+1])); | |
119 | index += len+3; | |
120 | } | |
121 | putc ('\n'); | |
122 | /* delayed reboot */ | |
123 | for (i=20; i>0; i--) { | |
124 | printf("Rebooting in %2d seconds \r",i); | |
125 | for (index=0;index<1000;index++) | |
126 | udelay(1000); | |
127 | } | |
128 | putc ('\n'); | |
129 | do_reset(NULL, 0, 0, NULL); | |
130 | } | |
131 | ||
132 | puts("FPGA: "); | |
133 | ||
134 | /* display infos on fpgaimage */ | |
135 | index = 15; | |
136 | for (i=0; i<4; i++) { | |
137 | len = dst[index]; | |
138 | printf("%s ", &(dst[index+1])); | |
139 | index += len+3; | |
140 | } | |
141 | putc ('\n'); | |
142 | ||
143 | free(dst); | |
144 | ||
145 | /* | |
146 | * Reset FPGA via FPGA_DATA pin | |
147 | */ | |
148 | SET_FPGA(FPGA_PRG | FPGA_CLK); | |
149 | udelay(1000); /* wait 1ms */ | |
150 | SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); | |
151 | udelay(1000); /* wait 1ms */ | |
152 | ||
153 | /* | |
154 | * Reset external DUARTs | |
155 | */ | |
6d0f6bcf | 156 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); |
c93f7096 | 157 | udelay(10); /* wait 10us */ |
6d0f6bcf | 158 | out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); |
c93f7096 SR |
159 | udelay(1000); /* wait 1ms */ |
160 | ||
c93f7096 SR |
161 | /* |
162 | * Enable interrupts in exar duart mcr[3] | |
163 | */ | |
049216f0 MF |
164 | out_8((void *)(DUART0_BA + 4), 0x08); |
165 | out_8((void *)(DUART1_BA + 4), 0x08); | |
166 | out_8((void *)(DUART2_BA + 4), 0x08); | |
167 | out_8((void *)(DUART3_BA + 4), 0x08); | |
c93f7096 SR |
168 | |
169 | return (0); | |
170 | } | |
171 | ||
172 | ||
173 | /* | |
174 | * Check Board Identity: | |
175 | */ | |
176 | ||
177 | int checkboard (void) | |
178 | { | |
77ddac94 | 179 | char str[64]; |
c93f7096 SR |
180 | int i = getenv_r ("serial#", str, sizeof(str)); |
181 | ||
182 | puts ("Board: "); | |
183 | ||
184 | if (i == -1) { | |
185 | puts ("### No HW ID - assuming ASH405"); | |
186 | } else { | |
187 | puts(str); | |
188 | } | |
189 | ||
190 | putc ('\n'); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
bd84ee4c | 195 | void reset_phy(void) |
c93f7096 | 196 | { |
bd84ee4c | 197 | #ifdef CONFIG_LXT971_NO_SLEEP |
bd84ee4c MF |
198 | /* |
199 | * Disable sleep mode in LXT971 | |
200 | */ | |
201 | lxt971_no_sleep(); | |
c93f7096 | 202 | #endif |
bd84ee4c | 203 | } |