]>
Commit | Line | Data |
---|---|---|
153d511e WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include "canbt.h" | |
26 | #include <asm/processor.h> | |
049216f0 | 27 | #include <asm/io.h> |
153d511e | 28 | #include <command.h> |
8bde7f77 | 29 | |
d87080b7 | 30 | DECLARE_GLOBAL_DATA_PTR; |
8bde7f77 WD |
31 | |
32 | /*cmd_boot.c*/ | |
33 | extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); | |
34 | ||
153d511e WD |
35 | |
36 | /* ------------------------------------------------------------------------- */ | |
37 | ||
38 | #if 0 | |
39 | #define FPGA_DEBUG | |
40 | #endif | |
41 | ||
42 | /* fpga configuration data */ | |
43 | const unsigned char fpgadata[] = { | |
44 | #include "fpgadata.c" | |
45 | }; | |
46 | ||
47 | /* | |
48 | * include common fpga code (for esd boards) | |
49 | */ | |
50 | #include "../common/fpga.c" | |
51 | ||
52 | ||
c837dcb1 | 53 | int board_early_init_f (void) |
153d511e | 54 | { |
d1c3b275 | 55 | unsigned long CPC0_CR0Reg; |
153d511e WD |
56 | int index, len, i; |
57 | int status; | |
58 | ||
59 | /* | |
60 | * Setup GPIO pins | |
61 | */ | |
d1c3b275 SR |
62 | CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff; |
63 | CPC0_CR0Reg |= 0x0070f000; | |
64 | mtdcr (CPC0_CR0, CPC0_CR0Reg); | |
153d511e WD |
65 | |
66 | #ifdef FPGA_DEBUG | |
67 | /* set up serial port with default baudrate */ | |
68 | (void) get_clocks (); | |
69 | gd->baudrate = CONFIG_BAUDRATE; | |
70 | serial_init (); | |
71 | console_init_f (); | |
72 | #endif | |
73 | ||
74 | /* | |
75 | * Boot onboard FPGA | |
76 | */ | |
77 | status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); | |
78 | if (status != 0) { | |
79 | /* booting FPGA failed */ | |
80 | #ifndef FPGA_DEBUG | |
81 | /* set up serial port with default baudrate */ | |
82 | (void) get_clocks (); | |
83 | gd->baudrate = CONFIG_BAUDRATE; | |
84 | serial_init (); | |
85 | console_init_f (); | |
86 | #endif | |
87 | printf ("\nFPGA: Booting failed "); | |
88 | switch (status) { | |
89 | case ERROR_FPGA_PRG_INIT_LOW: | |
90 | printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); | |
91 | break; | |
92 | case ERROR_FPGA_PRG_INIT_HIGH: | |
93 | printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); | |
94 | break; | |
95 | case ERROR_FPGA_PRG_DONE: | |
96 | printf ("(Timeout: DONE not high after programming FPGA)\n "); | |
97 | break; | |
98 | } | |
99 | ||
100 | /* display infos on fpgaimage */ | |
101 | index = 15; | |
102 | for (i = 0; i < 4; i++) { | |
103 | len = fpgadata[index]; | |
104 | printf ("FPGA: %s\n", &(fpgadata[index + 1])); | |
105 | index += len + 3; | |
106 | } | |
107 | putc ('\n'); | |
108 | /* delayed reboot */ | |
109 | for (i = 20; i > 0; i--) { | |
110 | printf ("Rebooting in %2d seconds \r", i); | |
111 | for (index = 0; index < 1000; index++) | |
112 | udelay (1000); | |
113 | } | |
114 | putc ('\n'); | |
115 | do_reset (NULL, 0, 0, NULL); | |
116 | } | |
117 | ||
118 | /* | |
119 | * Setup port pins for normal operation | |
120 | */ | |
049216f0 MF |
121 | out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ |
122 | out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */ | |
123 | out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */ | |
153d511e WD |
124 | |
125 | /* | |
126 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
127 | * IRQ 16 405GP internally generated; active low; level sensitive | |
128 | * IRQ 17-24 RESERVED | |
129 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
130 | * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive | |
131 | * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive | |
132 | * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive | |
133 | * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
134 | * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive | |
135 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
136 | */ | |
137 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
138 | mtdcr (uicer, 0x00000000); /* disable all ints */ | |
139 | mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ | |
140 | mtdcr (uicpr, 0xFFFFFF81); /* set int polarities */ | |
141 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ | |
142 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
143 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | ||
149 | /* ------------------------------------------------------------------------- */ | |
150 | ||
151 | /* | |
152 | * Check Board Identity: | |
153 | */ | |
154 | ||
155 | int checkboard (void) | |
156 | { | |
157 | int index; | |
158 | int len; | |
77ddac94 | 159 | char str[64]; |
153d511e WD |
160 | int i = getenv_r ("serial#", str, sizeof (str)); |
161 | ||
162 | puts ("Board: "); | |
163 | ||
164 | if (!i || strncmp (str, "CANBT", 5)) { | |
165 | puts ("### No HW ID - assuming CANBT\n"); | |
166 | return (0); | |
167 | } | |
168 | ||
169 | puts (str); | |
170 | ||
171 | puts ("\nFPGA: "); | |
172 | ||
173 | /* display infos on fpgaimage */ | |
174 | index = 15; | |
175 | for (i = 0; i < 4; i++) { | |
176 | len = fpgadata[index]; | |
177 | printf ("%s ", &(fpgadata[index + 1])); | |
178 | index += len + 3; | |
179 | } | |
180 | ||
181 | putc ('\n'); | |
182 | ||
183 | return 0; | |
184 | } |