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Commit | Line | Data |
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b9233fe5 MF |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b9233fe5 MF |
6 | */ |
7 | ||
8 | /* | |
9 | * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz) | |
10 | * Memory: DRAM (MCLK=40.000 MHz) | |
11 | */ | |
12 | static S1D_REGS regs_13505_640_480_16bpp[] = | |
13 | { | |
14 | {0x1B,0x00}, /* Miscellaneous Register */ | |
15 | {0x23,0x20}, /* Performance Enhancement Register 1 */ | |
16 | {0x01,0x30}, /* Memory Configuration Register */ | |
17 | {0x22,0x24}, /* Performance Enhancement Register 0 */ | |
18 | {0x02,0x25}, /* Panel Type Register */ | |
19 | {0x03,0x00}, /* MOD Rate Register */ | |
20 | {0x04,0x4F}, /* Horizontal Display Width Register */ | |
21 | {0x05,0x0c}, /* Horizontal Non-Display Period Register */ | |
22 | {0x06,0x00}, /* HRTC/FPLINE Start Position Register */ | |
23 | {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */ | |
24 | {0x08,0xDF}, /* Vertical Display Height Register 0 */ | |
25 | {0x09,0x01}, /* Vertical Display Height Register 1 */ | |
26 | {0x0A,0x3E}, /* Vertical Non-Display Period Register */ | |
27 | {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */ | |
28 | {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */ | |
29 | {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */ | |
30 | {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */ | |
31 | {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */ | |
32 | {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */ | |
33 | {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */ | |
34 | {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */ | |
35 | {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */ | |
36 | {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */ | |
37 | {0x16,0x80}, /* Memory Address Offset Register 0 */ | |
38 | {0x17,0x02}, /* Memory Address Offset Register 1 */ | |
39 | {0x18,0x00}, /* Pixel Panning Register */ | |
40 | {0x19,0x01}, /* Clock Configuration Register */ | |
41 | {0x1A,0x00}, /* Power Save Configuration Register */ | |
42 | {0x1C,0x00}, /* MD Configuration Readback Register 0 */ | |
43 | {0x1E,0x06}, /* General IO Pins Configuration Register 0 */ | |
44 | {0x1F,0x00}, /* General IO Pins Configuration Register 1 */ | |
45 | {0x20,0x00}, /* General IO Pins Control Register 0 */ | |
46 | {0x21,0x00}, /* General IO Pins Control Register 1 */ | |
47 | {0x23,0x20}, /* Performance Enhancement Register 1 */ | |
48 | {0x0D,0x15}, /* Display Mode Register */ | |
49 | }; |