[people/ms/u-boot.git] / board / esd / cpci405 / cpci405.c

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <cmd_boot.h>
#include <malloc.h>

/* ------------------------------------------------------------------------- */

#if 0
#define FPGA_DEBUG
#endif

/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] =
{
#ifdef CONFIG_CPCI405_VER2
# include "fpgadata_cpci4052.c"
#else
# include "fpgadata_cpci405.c"
#endif
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


/* Prototypes */
int cpci405_version(void);
int gunzip(void *, int, unsigned char *, int *);


int board_pre_init (void)
{
#ifndef CONFIG_CPCI405_VER2
	int index, len, i;
	int status;
#endif

#ifdef FPGA_DEBUG
	DECLARE_GLOBAL_DATA_PTR;

	/* set up serial port with default baudrate */
	(void) get_clocks ();
	gd->baudrate = CONFIG_BAUDRATE;
	serial_init ();
	console_init_f();
#endif

	/*
	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
	 */
	out32(IBM405GP_GPIO0_ODR, 0x00000000);        /* no open drain pins      */
	out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
	out32(IBM405GP_GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
	out32(IBM405GP_GPIO0_OR, 0);                  /* pull prg low            */

	/*
	 * Boot onboard FPGA
	 */
#ifndef CONFIG_CPCI405_VER2
	if (cpci405_version() == 1) {
		status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
		if (status != 0) {
			/* booting FPGA failed */
#ifndef FPGA_DEBUG
			DECLARE_GLOBAL_DATA_PTR;

			/* set up serial port with default baudrate */
			(void) get_clocks ();
			gd->baudrate = CONFIG_BAUDRATE;
			serial_init ();
			console_init_f();
#endif
			printf("\nFPGA: Booting failed ");
			switch (status) {
			case ERROR_FPGA_PRG_INIT_LOW:
				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_INIT_HIGH:
				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_DONE:
				printf("(Timeout: DONE not high after programming FPGA)\n ");
				break;
			}

			/* display infos on fpgaimage */
			index = 15;
			for (i=0; i<4; i++) {
				len = fpgadata[index];
				printf("FPGA: %s\n", &(fpgadata[index+1]));
				index += len+3;
			}
			putc ('\n');
			/* delayed reboot */
			for (i=20; i>0; i--) {
				printf("Rebooting in %2d seconds \r",i);
				for (index=0;index<1000;index++)
					udelay(1000);
			}
			putc ('\n');
			do_reset(NULL, 0, 0, NULL);
		}
	}
#endif /* !CONFIG_CPCI405_VER2 */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(uicer, 0x00000000);       /* disable all ints */
	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
	if (cpci405_version() == 3) {
		mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
	} else {
		mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
	}
	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */

	return 0;
}


/* ------------------------------------------------------------------------- */

int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
	return 0;                       /* no, board is cpci405 */
#else
	if ((*(unsigned char *)0xf0000400 == 0x00) &&
	    (*(unsigned char *)0xf0000401 == 0x01))
		return 0;               /* no, board is cpci405 */
	else
		return -1;              /* yes, board is cterm-m2 */
#endif
}


int cpci405_host(void)
{
	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
		return -1;              /* yes, board is cpci405 host */
	else
		return 0;               /* no, board is cpci405 adapter */
}


int cpci405_version(void)
{
	unsigned long cntrl0Reg;
	unsigned long value;

	/*
	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
	out32(IBM405GP_GPIO0_ODR, in32(IBM405GP_GPIO0_ODR) & ~0x00180000);
	out32(IBM405GP_GPIO0_TCR, in32(IBM405GP_GPIO0_TCR) & ~0x00180000);
	udelay(1000);                   /* wait some time before reading input */
	value = in32(IBM405GP_GPIO0_IR) & 0x00180000;       /* get config bits */

	/*
	 * Restore GPIO settings
	 */
	mtdcr(cntrl0, cntrl0Reg);

	switch (value) {
	case 0x00180000:
		/* CS2==1 && CS3==1 -> version 1 */
		return 1;
	case 0x00080000:
		/* CS2==0 && CS3==1 -> version 2 */
		return 2;
	case 0x00100000:
		/* CS2==1 && CS3==0 -> version 3 */
		return 3;
	case 0x00000000:
		/* CS2==0 && CS3==0 -> version 4 */
		return 4;
	default:
		/* should not be reached! */
		return 2;
	}
}


int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}


int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	bd_t *bd = gd->bd;
	char *	tmp;                    /* Temporary char pointer      */

#ifdef CONFIG_CPCI405_VER2
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long cntrl0Reg;

	/*
	 * On CPCI-405 version 2 the environment is saved in eeprom!
	 * FPGA can be gzip compressed (malloc) and booted this late.
	 */

	if (cpci405_version() >= 2) {
		/*
		 * Setup GPIO pins (CS6+CS7 as GPIO)
		 */
		cntrl0Reg = mfdcr(cntrl0);
		mtdcr(cntrl0, cntrl0Reg | 0x00300000);

		dst = malloc(CFG_FPGA_MAX_SIZE);
		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
			printf ("GUNZIP ERROR - must RESET board to recover\n");
			do_reset (NULL, 0, 0, NULL);
		}

		status = fpga_boot(dst, len);
		if (status != 0) {
			printf("\nFPGA: Booting failed ");
			switch (status) {
			case ERROR_FPGA_PRG_INIT_LOW:
				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_INIT_HIGH:
				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_DONE:
				printf("(Timeout: DONE not high after programming FPGA)\n ");
				break;
			}

			/* display infos on fpgaimage */
			index = 15;
			for (i=0; i<4; i++) {
				len = dst[index];
				printf("FPGA: %s\n", &(dst[index+1]));
				index += len+3;
			}
			putc ('\n');
			/* delayed reboot */
			for (i=20; i>0; i--) {
				printf("Rebooting in %2d seconds \r",i);
				for (index=0;index<1000;index++)
					udelay(1000);
			}
			putc ('\n');
			do_reset(NULL, 0, 0, NULL);
		}

		/* restore gpio/cs settings */
		mtdcr(cntrl0, cntrl0Reg);

		puts("FPGA:  ");

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("%s ", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');

		free(dst);

		/*
		 * Reset FPGA via FPGA_DATA pin
		 */
		SET_FPGA(FPGA_PRG | FPGA_CLK);
		udelay(1000); /* wait 1ms */
		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
		udelay(1000); /* wait 1ms */

		if (cpci405_version() == 3) {
			volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
			volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;

			/*
			 * Enable outputs in fpga on version 3 board
			 */
			*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;

			/*
			 * Set outputs to 0
			 */
			*leds = 0x00;

			/*
			 * Reset external DUART
			 */
			*fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
			udelay(100);
			*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
		}
	}
	else {
		puts("\n*** U-Boot Version does not match Board Version!\n");
		puts("*** CPCI-405 Version 1.x detected!\n");
		puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
	}

#else /* CONFIG_CPCI405_VER2 */

	/*
	 * Generate last byte of ip-addr from code-plug @ 0xf0000400
	 */
	if (ctermm2()) {
		char str[32];
		unsigned char ipbyte = *(unsigned char *)0xf0000400;

		/*
		 * Only overwrite ip-addr with allowed values
		 */
		if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
			bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
			sprintf(str, "%ld.%ld.%ld.%ld",
				(bd->bi_ip_addr & 0xff000000) >> 24,
				(bd->bi_ip_addr & 0x00ff0000) >> 16,
				(bd->bi_ip_addr & 0x0000ff00) >> 8,
				(bd->bi_ip_addr & 0x000000ff));
			setenv("ipaddr", str);
		}
	}

	if (cpci405_version() >= 2) {
		puts("\n*** U-Boot Version does not match Board Version!\n");
		puts("*** CPCI-405 Board Version 2.x detected!\n");
		puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
	}

#endif /* CONFIG_CPCI405_VER2 */

	/*
	 * Write ethernet addr in NVRAM for VxWorks
	 */
	tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
	memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
#ifndef CONFIG_CPCI405_VER2
	int index;
	int len;
#endif
	unsigned char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));
	unsigned short ver;

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming CPCI405");
	} else {
		puts(str);
	}

	ver = cpci405_version();
	printf(" (Ver %d.x, ", ver);

#if 0 /* test-only */
	if (ver >= 2) {
		volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;

		if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
			puts ("FLASH Bank B, ");
		} else {
			puts ("FLASH Bank A, ");
		}
	}
#endif

	if (ctermm2()) {
		printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
	} else {
		if (cpci405_host()) {
			puts ("PCI Host Version)");
		} else {
			puts ("PCI Adapter Version)");
		}
	}

#ifndef CONFIG_CPCI405_VER2
	puts ("\nFPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = fpgadata[index];
		printf("%s ", &(fpgadata[index+1]));
		index += len+3;
	}
#endif

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET

void ide_set_reset(int on)
{
	volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;

	/*
	 * Assert or deassert CompactFlash Reset Pin
	 */
	if (on) {		/* assert RESET */
		*fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
	} else {		/* release RESET */
		*fpga_mode |= CFG_FPGA_MODE_CF_RESET;
	}
}

#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */

/* ------------------------------------------------------------------------- */
Commit	Line	Data
c609719b	1	/*
6f4474e8	2	* (C) Copyright 2001-2003
c609719b WD	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <cmd_boot.h>
	28	#include <malloc.h>
	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	#if 0
	33	#define FPGA_DEBUG
	34	#endif
	35
	36	/* fpga configuration data - generated by bin2cc */
	37	const unsigned char fpgadata[] =
	38	{
	39	#ifdef CONFIG_CPCI405_VER2
	40	# include "fpgadata_cpci4052.c"
	41	#else
	42	# include "fpgadata_cpci405.c"
	43	#endif
	44	};
	45
	46	/*
	47	* include common fpga code (for esd boards)
	48	*/
	49	#include "../common/fpga.c"
	50
	51
	52	/* Prototypes */
6f4474e8	53	int cpci405_version(void);
c609719b WD	54	int gunzip(void , int, unsigned char , int *);
	55
	56
	57	int board_pre_init (void)
	58	{
	59	#ifndef CONFIG_CPCI405_VER2
	60	int index, len, i;
	61	int status;
	62	#endif
	63
	64	#ifdef FPGA_DEBUG
	65	DECLARE_GLOBAL_DATA_PTR;
	66
	67	/* set up serial port with default baudrate */
	68	(void) get_clocks ();
	69	gd->baudrate = CONFIG_BAUDRATE;
	70	serial_init ();
	71	console_init_f();
	72	#endif
	73
	74	/*
	75	* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
	76	*/
	77	out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
	78	out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
	79	out32(IBM405GP_GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
	80	out32(IBM405GP_GPIO0_OR, 0); /* pull prg low */
	81
	82	/*
	83	* Boot onboard FPGA
	84	*/
	85	#ifndef CONFIG_CPCI405_VER2
6f4474e8	86	if (cpci405_version() == 1) {
c609719b WD	87	status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
	88	if (status != 0) {
	89	/* booting FPGA failed */
	90	#ifndef FPGA_DEBUG
	91	DECLARE_GLOBAL_DATA_PTR;
	92
	93	/* set up serial port with default baudrate */
	94	(void) get_clocks ();
	95	gd->baudrate = CONFIG_BAUDRATE;
	96	serial_init ();
	97	console_init_f();
	98	#endif
	99	printf("\nFPGA: Booting failed ");
	100	switch (status) {
	101	case ERROR_FPGA_PRG_INIT_LOW:
	102	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	103	break;
	104	case ERROR_FPGA_PRG_INIT_HIGH:
	105	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	106	break;
	107	case ERROR_FPGA_PRG_DONE:
	108	printf("(Timeout: DONE not high after programming FPGA)\n ");
	109	break;
	110	}
	111
	112	/* display infos on fpgaimage */
	113	index = 15;
	114	for (i=0; i<4; i++) {
	115	len = fpgadata[index];
	116	printf("FPGA: %s\n", &(fpgadata[index+1]));
	117	index += len+3;
	118	}
	119	putc ('\n');
	120	/* delayed reboot */
	121	for (i=20; i>0; i--) {
	122	printf("Rebooting in %2d seconds \r",i);
	123	for (index=0;index<1000;index++)
	124	udelay(1000);
	125	}
	126	putc ('\n');
	127	do_reset(NULL, 0, 0, NULL);
	128	}
	129	}
	130	#endif /* !CONFIG_CPCI405_VER2 */
	131
	132	/*
	133	* IRQ 0-15 405GP internally generated; active high; level sensitive
	134	* IRQ 16 405GP internally generated; active low; level sensitive
	135	* IRQ 17-24 RESERVED
	136	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	137	* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
	138	* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	139	* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	140	* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	141	* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	142	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	143	*/
	144	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	145	mtdcr(uicer, 0x00000000); /* disable all ints */
	146	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
6f4474e8 SR	147	if (cpci405_version() == 3) {
	148	mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
	149	} else {
	150	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
	151	}
c609719b WD	152	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	153	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	154	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	155
	156	return 0;
	157	}
	158
	159
	160	/* ------------------------------------------------------------------------- */
	161
	162	int ctermm2(void)
	163	{
	164	#ifdef CONFIG_CPCI405_VER2
	165	return 0; /* no, board is cpci405 */
	166	#else
	167	if (((unsigned char )0xf0000400 == 0x00) &&
	168	((unsigned char )0xf0000401 == 0x01))
	169	return 0; /* no, board is cpci405 */
	170	else
	171	return -1; /* yes, board is cterm-m2 */
	172	#endif
	173	}
	174
	175
	176	int cpci405_host(void)
	177	{
	178	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
	179	return -1; /* yes, board is cpci405 host */
	180	else
	181	return 0; /* no, board is cpci405 adapter */
	182	}
	183
	184
6f4474e8	185	int cpci405_version(void)
c609719b WD	186	{
	187	unsigned long cntrl0Reg;
	188	unsigned long value;
	189
	190	/*
6f4474e8	191	* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
c609719b WD	192	*/
c609719b WD	193	cntrl0Reg = mfdcr(cntrl0);
6f4474e8 SR	194	mtdcr(cntrl0, cntrl0Reg \| 0x03000000);
	195	out32(IBM405GP_GPIO0_ODR, in32(IBM405GP_GPIO0_ODR) & ~0x00180000);
	196	out32(IBM405GP_GPIO0_TCR, in32(IBM405GP_GPIO0_TCR) & ~0x00180000);
c609719b	197	udelay(1000); /* wait some time before reading input */
6f4474e8	198	value = in32(IBM405GP_GPIO0_IR) & 0x00180000; /* get config bits */
c609719b WD	199
c609719b WD	200	/*
6f4474e8	201	* Restore GPIO settings
c609719b WD	202	*/
	203	mtdcr(cntrl0, cntrl0Reg);
	204
6f4474e8 SR	205	switch (value) {
	206	case 0x00180000:
	207	/* CS2==1 && CS3==1 -> version 1 */
	208	return 1;
	209	case 0x00080000:
	210	/* CS2==0 && CS3==1 -> version 2 */
	211	return 2;
	212	case 0x00100000:
	213	/* CS2==1 && CS3==0 -> version 3 */
	214	return 3;
	215	case 0x00000000:
	216	/* CS2==0 && CS3==0 -> version 4 */
	217	return 4;
	218	default:
	219	/* should not be reached! */
	220	return 2;
	221	}
c609719b WD	222	}
	223
	224
	225	int misc_init_f (void)
	226	{
	227	return 0; /* dummy implementation */
	228	}
	229
	230
	231	int misc_init_r (void)
	232	{
	233	DECLARE_GLOBAL_DATA_PTR;
	234
	235	bd_t *bd = gd->bd;
	236	char * tmp; /* Temporary char pointer */
	237
	238	#ifdef CONFIG_CPCI405_VER2
	239	unsigned char *dst;
	240	ulong len = sizeof(fpgadata);
	241	int status;
	242	int index;
	243	int i;
	244	unsigned long cntrl0Reg;
	245
	246	/*
	247	* On CPCI-405 version 2 the environment is saved in eeprom!
	248	* FPGA can be gzip compressed (malloc) and booted this late.
	249	*/
	250
6f4474e8	251	if (cpci405_version() >= 2) {
c609719b WD	252	/*
	253	* Setup GPIO pins (CS6+CS7 as GPIO)
	254	*/
	255	cntrl0Reg = mfdcr(cntrl0);
	256	mtdcr(cntrl0, cntrl0Reg \| 0x00300000);
	257
	258	dst = malloc(CFG_FPGA_MAX_SIZE);
	259	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar )fpgadata, (int )&len) != 0) {
	260	printf ("GUNZIP ERROR - must RESET board to recover\n");
	261	do_reset (NULL, 0, 0, NULL);
	262	}
	263
	264	status = fpga_boot(dst, len);
	265	if (status != 0) {
	266	printf("\nFPGA: Booting failed ");
	267	switch (status) {
	268	case ERROR_FPGA_PRG_INIT_LOW:
	269	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	270	break;
	271	case ERROR_FPGA_PRG_INIT_HIGH:
	272	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	273	break;
	274	case ERROR_FPGA_PRG_DONE:
	275	printf("(Timeout: DONE not high after programming FPGA)\n ");
	276	break;
	277	}
	278
	279	/* display infos on fpgaimage */
	280	index = 15;
	281	for (i=0; i<4; i++) {
	282	len = dst[index];
	283	printf("FPGA: %s\n", &(dst[index+1]));
	284	index += len+3;
	285	}
	286	putc ('\n');
	287	/* delayed reboot */
	288	for (i=20; i>0; i--) {
	289	printf("Rebooting in %2d seconds \r",i);
	290	for (index=0;index<1000;index++)
	291	udelay(1000);
	292	}
	293	putc ('\n');
	294	do_reset(NULL, 0, 0, NULL);
	295	}
	296
	297	/* restore gpio/cs settings */
	298	mtdcr(cntrl0, cntrl0Reg);
	299
	300	puts("FPGA: ");
	301
	302	/* display infos on fpgaimage */
	303	index = 15;
	304	for (i=0; i<4; i++) {
	305	len = dst[index];
	306	printf("%s ", &(dst[index+1]));
	307	index += len+3;
	308	}
	309	putc ('\n');
	310
	311	free(dst);
6f4474e8 SR	312
	313	/*
	314	* Reset FPGA via FPGA_DATA pin
	315	*/
	316	SET_FPGA(FPGA_PRG \| FPGA_CLK);
	317	udelay(1000); /* wait 1ms */
	318	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
	319	udelay(1000); /* wait 1ms */
	320
	321	if (cpci405_version() == 3) {
	322	volatile unsigned short fpga_mode = (unsigned short )CFG_FPGA_BASE_ADDR;
	323	volatile unsigned char leds = (unsigned char )CFG_LED_ADDR;
	324
	325	/*
	326	* Enable outputs in fpga on version 3 board
	327	*/
	328	*fpga_mode \|= CFG_FPGA_MODE_ENABLE_OUTPUT;
	329
	330	/*
	331	* Set outputs to 0
	332	*/
	333	*leds = 0x00;
	334
	335	/*
	336	* Reset external DUART
	337	*/
	338	*fpga_mode \|= CFG_FPGA_MODE_DUART_RESET;
	339	udelay(100);
	340	*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
	341	}
c609719b WD	342	}
c609719b WD	343	else {
6f4474e8 SR	344	puts("\n*** U-Boot Version does not match Board Version!\n");
	345	puts("*** CPCI-405 Version 1.x detected!\n");
	346	puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
c609719b WD	347	}
	348
	349	#else /* CONFIG_CPCI405_VER2 */
	350
	351	/*
	352	* Generate last byte of ip-addr from code-plug @ 0xf0000400
	353	*/
	354	if (ctermm2()) {
	355	char str[32];
	356	unsigned char ipbyte = (unsigned char )0xf0000400;
	357
	358	/*
	359	* Only overwrite ip-addr with allowed values
	360	*/
	361	if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
	362	bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) \| ipbyte;
	363	sprintf(str, "%ld.%ld.%ld.%ld",
	364	(bd->bi_ip_addr & 0xff000000) >> 24,
	365	(bd->bi_ip_addr & 0x00ff0000) >> 16,
	366	(bd->bi_ip_addr & 0x0000ff00) >> 8,
	367	(bd->bi_ip_addr & 0x000000ff));
	368	setenv("ipaddr", str);
	369	}
	370	}
	371
6f4474e8 SR	372	if (cpci405_version() >= 2) {
	373	puts("\n*** U-Boot Version does not match Board Version!\n");
	374	puts("*** CPCI-405 Board Version 2.x detected!\n");
	375	puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
c609719b WD	376	}
	377
	378	#endif /* CONFIG_CPCI405_VER2 */
	379
	380	/*
	381	* Write ethernet addr in NVRAM for VxWorks
	382	*/
	383	tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
	384	memcpy( (char )tmp, (char )&bd->bi_enetaddr[0], 6 );
	385	return (0);
	386	}
	387
	388
	389	/*
	390	* Check Board Identity:
	391	*/
	392
	393	int checkboard (void)
	394	{
	395	#ifndef CONFIG_CPCI405_VER2
	396	int index;
	397	int len;
	398	#endif
	399	unsigned char str[64];
	400	int i = getenv_r ("serial#", str, sizeof(str));
6f4474e8	401	unsigned short ver;
c609719b WD	402
	403	puts ("Board: ");
	404
	405	if (i == -1) {
	406	puts ("### No HW ID - assuming CPCI405");
	407	} else {
	408	puts(str);
	409	}
	410
6f4474e8 SR	411	ver = cpci405_version();
6f4474e8 SR	412	printf(" (Ver %d.x, ", ver);
c609719b	413
6f4474e8 SR	414	#if 0 /* test-only */
	415	if (ver >= 2) {
	416	volatile u16 fpga_status = (u16 )CFG_FPGA_BASE_ADDR + 1;
	417
	418	if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
	419	puts ("FLASH Bank B, ");
	420	} else {
	421	puts ("FLASH Bank A, ");
	422	}
	423	}
c609719b WD	424	#endif
	425
	426	if (ctermm2()) {
	427	printf("CTERM-M2 - Id=0x%02x)", (unsigned char )0xf0000400);
	428	} else {
	429	if (cpci405_host()) {
	430	puts ("PCI Host Version)");
	431	} else {
	432	puts ("PCI Adapter Version)");
	433	}
	434	}
	435
	436	#ifndef CONFIG_CPCI405_VER2
	437	puts ("\nFPGA: ");
	438
	439	/* display infos on fpgaimage */
	440	index = 15;
	441	for (i=0; i<4; i++) {
	442	len = fpgadata[index];
	443	printf("%s ", &(fpgadata[index+1]));
	444	index += len+3;
	445	}
	446	#endif
	447
	448	putc ('\n');
	449
	450	return 0;
	451	}
	452
	453	/* ------------------------------------------------------------------------- */
	454
	455	long int initdram (int board_type)
	456	{
	457	unsigned long val;
	458
	459	mtdcr(memcfga, mem_mb0cf);
	460	val = mfdcr(memcfgd);
	461
	462	#if 0
	463	printf("\nmb0cf=%x\n", val); /* test-only */
	464	printf("strap=%x\n", mfdcr(strap)); /* test-only */
	465	#endif
	466
	467	return (410241024 << ((val & 0x000e0000) >> 17));
	468	}
	469
	470	/* ------------------------------------------------------------------------- */
	471
	472	int testdram (void)
	473	{
	474	/* TODO: XXX XXX XXX */
	475	printf ("test: 16 MB - ok\n");
	476
	477	return (0);
	478	}
	479
	480	/* ------------------------------------------------------------------------- */
	481
	482	#ifdef CONFIG_CPCI405_VER2
	483	#ifdef CONFIG_IDE_RESET
	484
	485	void ide_set_reset(int on)
	486	{
	487	volatile unsigned short fpga_mode = (unsigned short )CFG_FPGA_BASE_ADDR;
488
489	/*
490	* Assert or deassert CompactFlash Reset Pin
491	*/
492	if (on) { /* assert RESET */
493	*fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
494	} else { /* release RESET */
495	*fpga_mode \|= CFG_FPGA_MODE_CF_RESET;
496	}
497	}
498
499	#endif /* CONFIG_IDE_RESET */
500	#endif /* CONFIG_CPCI405_VER2 */
501
502	/* ------------------------------------------------------------------------- */