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771e05be SR |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Ingo Assmus <ingo.assmus@keymile.com> | |
4 | * for cpci750 Reinhard Arlt | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
771e05be SR |
7 | */ |
8 | ||
9 | /* | |
10 | * main board support/init for the cpci750. | |
11 | */ | |
12 | ||
13 | #ifndef __64360_H__ | |
14 | #define __64360_H__ | |
15 | ||
16 | /* CPU Configuration bits */ | |
17 | #define CPU_CONF_ADDR_MISS_EN (1 << 8) | |
18 | #define CPU_CONF_SINGLE_CPU (1 << 11) | |
19 | #define CPU_CONF_ENDIANESS (1 << 12) | |
20 | #define CPU_CONF_PIPELINE (1 << 13) | |
21 | #define CPU_CONF_STOP_RETRY (1 << 17) | |
22 | #define CPU_CONF_MULTI_DECODE (1 << 18) | |
23 | #define CPU_CONF_DP_VALID (1 << 19) | |
24 | #define CPU_CONF_PERR_PROP (1 << 22) | |
25 | #define CPU_CONF_AACK_DELAY_2 (1 << 25) | |
26 | #define CPU_CONF_AP_VALID (1 << 26) | |
27 | #define CPU_CONF_REMAP_WR_DIS (1 << 27) | |
28 | ||
29 | /* CPU Master Control bits */ | |
30 | #define CPU_MAST_CTL_ARB_EN (1 << 8) | |
31 | #define CPU_MAST_CTL_MASK_BR_1 (1 << 9) | |
32 | #define CPU_MAST_CTL_M_WR_TRIG (1 << 10) | |
33 | #define CPU_MAST_CTL_M_RD_TRIG (1 << 11) | |
34 | #define CPU_MAST_CTL_CLEAN_BLK (1 << 12) | |
35 | #define CPU_MAST_CTL_FLUSH_BLK (1 << 13) | |
36 | ||
37 | #endif /* __64360_H__ */ |