projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 771e05be SR |
1 | /* |
| 2 | * (C) Copyright 2000 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 771e05be SR |
6 | */ |
| 7 | /* ide.c - ide support functions */ | |
| 8 | ||
| 9 | ||
| 10 | #include <common.h> | |
| 77a31854 | 11 | #if defined(CONFIG_CMD_IDE) |
| 771e05be SR |
12 | #include <ata.h> |
| 13 | #include <ide.h> | |
| 14 | #include <pci.h> | |
| 15 | ||
| 2b224609 RA |
16 | int cpci_hd_type; |
| 17 | ||
| 18 | int ata_device(int dev) | |
| 19 | { | |
| 20 | int retval; | |
| 21 | ||
| 22 | retval = (dev & 1) << 4; | |
| 23 | if (cpci_hd_type == 2) | |
| 24 | retval ^= 1 << 4; | |
| 25 | return retval; | |
| 26 | } | |
| 27 | ||
| 771e05be | 28 | |
| efe2a4d5 WD |
29 | int ide_preinit (void) |
| 30 | { | |
| 31 | int status; | |
| 32 | pci_dev_t devbusfn; | |
| 33 | int l; | |
| 771e05be | 34 | |
| efe2a4d5 | 35 | status = 1; |
| 2b224609 | 36 | cpci_hd_type = 0; |
| 58f10460 SR |
37 | if (CPCI750_SLAVE_TEST != 0) |
| 38 | return status; | |
| 6d0f6bcf | 39 | for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { |
| efe2a4d5 WD |
40 | ide_bus_offset[l] = -ATA_STATUS; |
| 41 | } | |
| 42 | devbusfn = pci_find_device (0x1103, 0x0004, 0); | |
| 2b224609 RA |
43 | if (devbusfn != -1) { |
| 44 | cpci_hd_type = 1; | |
| 45 | } else { | |
| 2d78074d | 46 | devbusfn = pci_find_device (0x1095, 0x3114, 0); |
| 2b224609 RA |
47 | if (devbusfn != -1) { |
| 48 | cpci_hd_type = 2; | |
| 49 | } | |
| 50 | } | |
| efe2a4d5 | 51 | if (devbusfn != -1) { |
| 97138fc4 WD |
52 | ulong *ide_bus_offset_ptr; |
| 53 | ||
| efe2a4d5 | 54 | status = 0; |
| 771e05be | 55 | |
| 97138fc4 | 56 | ide_bus_offset_ptr = &ide_bus_offset[0]; |
| efe2a4d5 | 57 | pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, |
| 97138fc4 | 58 | (u32 *)ide_bus_offset_ptr); |
| efe2a4d5 | 59 | ide_bus_offset[0] &= 0xfffffffe; |
| 6d0f6bcf | 60 | ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; |
| 97138fc4 | 61 | ide_bus_offset_ptr = &ide_bus_offset[1]; |
| efe2a4d5 | 62 | pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, |
| 97138fc4 | 63 | (u32 *)ide_bus_offset_ptr); |
| efe2a4d5 | 64 | ide_bus_offset[1] &= 0xfffffffe; |
| 6d0f6bcf | 65 | ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; |
| efe2a4d5 | 66 | } |
| 58f10460 | 67 | return status; |
| efe2a4d5 | 68 | } |
| 771e05be | 69 | |
| efe2a4d5 WD |
70 | void ide_set_reset (int flag) { |
| 71 | return; | |
| 72 | } | |
| 771e05be SR |
73 | |
| 74 | #endif /* of CONFIG_CMDS_IDE */ |