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Commit | Line | Data |
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affae2bf WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
affae2bf WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
10 | #include <pci.h> | |
049216f0 | 11 | #include <asm/io.h> |
affae2bf WD |
12 | |
13 | #define OK 0 | |
14 | #define ERROR (-1) | |
15 | ||
affae2bf WD |
16 | extern u_long pci9054_iobase; |
17 | ||
18 | ||
19 | /*************************************************************************** | |
20 | * | |
21 | * Routines for PLX PCI9054 eeprom access | |
22 | * | |
23 | */ | |
24 | ||
8bde7f77 | 25 | static unsigned int PciEepromReadLongVPD (int offs) |
affae2bf | 26 | { |
8bde7f77 WD |
27 | unsigned int value; |
28 | unsigned int ret; | |
29 | int count; | |
30 | ||
6d0f6bcf | 31 | pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, |
8bde7f77 WD |
32 | (offs << 16) | 0x0003); |
33 | count = 0; | |
34 | ||
35 | for (;;) { | |
36 | udelay (10 * 1000); | |
6d0f6bcf | 37 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); |
8bde7f77 WD |
38 | if ((ret & 0x80000000) != 0) { |
39 | break; | |
40 | } else { | |
41 | count++; | |
42 | if (count > 10) { | |
43 | printf ("\nTimeout: ret=%08x - Please try again!\n", ret); | |
44 | break; | |
45 | } | |
46 | } | |
47 | } | |
48 | ||
6d0f6bcf | 49 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value); |
8bde7f77 WD |
50 | |
51 | return value; | |
affae2bf WD |
52 | } |
53 | ||
54 | ||
8bde7f77 | 55 | static int PciEepromWriteLongVPD (int offs, unsigned int value) |
affae2bf | 56 | { |
8bde7f77 WD |
57 | unsigned int ret; |
58 | int count; | |
59 | ||
6d0f6bcf JCPV |
60 | pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value); |
61 | pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, | |
8bde7f77 WD |
62 | (offs << 16) | 0x80000003); |
63 | count = 0; | |
64 | ||
65 | for (;;) { | |
66 | udelay (10 * 1000); | |
6d0f6bcf | 67 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); |
8bde7f77 WD |
68 | if ((ret & 0x80000000) == 0) { |
69 | break; | |
70 | } else { | |
71 | count++; | |
72 | if (count > 10) { | |
73 | printf ("\nTimeout: ret=%08x - Please try again!\n", ret); | |
74 | break; | |
75 | } | |
76 | } | |
77 | } | |
78 | ||
472d5460 | 79 | return true; |
affae2bf WD |
80 | } |
81 | ||
82 | ||
8bde7f77 | 83 | static void showPci9054 (void) |
affae2bf | 84 | { |
8bde7f77 WD |
85 | int val; |
86 | int l, i; | |
87 | ||
88 | /* read 9054-values */ | |
89 | for (l = 0; l < 6; l++) { | |
90 | printf ("%02x: ", l * 0x10); | |
91 | for (i = 0; i < 4; i++) { | |
6d0f6bcf | 92 | pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, |
8bde7f77 | 93 | l * 16 + i * 4, |
77ddac94 | 94 | (unsigned int *)&val); |
8bde7f77 WD |
95 | printf ("%08x ", val); |
96 | } | |
97 | printf ("\n"); | |
98 | } | |
99 | printf ("\n"); | |
100 | ||
101 | for (l = 0; l < 7; l++) { | |
102 | printf ("%02x: ", l * 0x10); | |
103 | for (i = 0; i < 4; i++) | |
104 | printf ("%08x ", | |
105 | PciEepromReadLongVPD ((i + l * 4) * 4)); | |
106 | printf ("\n"); | |
107 | } | |
108 | printf ("\n"); | |
affae2bf WD |
109 | } |
110 | ||
111 | ||
8bde7f77 | 112 | static void updatePci9054 (void) |
affae2bf | 113 | { |
8bde7f77 WD |
114 | /* |
115 | * Set EEPROM write-protect register to 0 | |
116 | */ | |
049216f0 MF |
117 | out_be32 ((void *)(pci9054_iobase + 0x0c), |
118 | in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); | |
affae2bf | 119 | |
8bde7f77 | 120 | /* Long Serial EEPROM Load Registers... */ |
b2776d3f SR |
121 | PciEepromWriteLongVPD (0x00, 0x905410b5); |
122 | PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ | |
123 | PciEepromWriteLongVPD (0x08, 0x28140100); | |
affae2bf | 124 | |
b2776d3f SR |
125 | PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ |
126 | PciEepromWriteLongVPD (0x10, 0x00000000); | |
affae2bf | 127 | |
8bde7f77 | 128 | /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ |
b2776d3f SR |
129 | PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ |
130 | PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ | |
affae2bf | 131 | |
b2776d3f SR |
132 | PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ |
133 | PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ | |
affae2bf | 134 | |
b2776d3f SR |
135 | PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ |
136 | PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ | |
affae2bf | 137 | |
b2776d3f | 138 | PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ |
affae2bf | 139 | |
b2776d3f SR |
140 | PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ |
141 | PciEepromWriteLongVPD (0x34, 0x00000000); | |
142 | PciEepromWriteLongVPD (0x38, 0x00000000); | |
affae2bf | 143 | |
b2776d3f SR |
144 | PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ |
145 | PciEepromWriteLongVPD (0x40, 0x00000000); | |
affae2bf | 146 | |
8bde7f77 | 147 | /* Extra Long Serial EEPROM Load Registers... */ |
b2776d3f | 148 | PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ |
affae2bf | 149 | |
8bde7f77 WD |
150 | /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ |
151 | /* Offset to LAS1: Group 1: 0x00040000 */ | |
152 | /* Group 2: 0x00080000 */ | |
153 | /* Group 3: 0x000c0000 */ | |
b2776d3f SR |
154 | PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ |
155 | PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ | |
156 | PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ | |
affae2bf | 157 | |
b2776d3f | 158 | PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ |
affae2bf | 159 | |
8bde7f77 | 160 | printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); |
affae2bf WD |
161 | } |
162 | ||
163 | ||
8bde7f77 | 164 | static void clearPci9054 (void) |
affae2bf | 165 | { |
8bde7f77 WD |
166 | /* |
167 | * Set EEPROM write-protect register to 0 | |
168 | */ | |
049216f0 MF |
169 | out_be32 ((void *)(pci9054_iobase + 0x0c), |
170 | in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); | |
affae2bf | 171 | |
8bde7f77 | 172 | /* Long Serial EEPROM Load Registers... */ |
b2776d3f SR |
173 | PciEepromWriteLongVPD (0x00, 0xffffffff); |
174 | PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ | |
affae2bf | 175 | |
8bde7f77 | 176 | printf ("Finished clearing PLX PCI9054 EEPROM!\n"); |
affae2bf WD |
177 | } |
178 | ||
179 | ||
180 | /* ------------------------------------------------------------------------- */ | |
8bde7f77 | 181 | int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, |
54841ab5 | 182 | char * const argv[]) |
affae2bf | 183 | { |
8bde7f77 WD |
184 | if (strcmp (argv[1], "info") == 0) { |
185 | showPci9054 (); | |
186 | return 0; | |
187 | } | |
188 | ||
189 | if (strcmp (argv[1], "update") == 0) { | |
190 | updatePci9054 (); | |
191 | return 0; | |
192 | } | |
193 | ||
194 | if (strcmp (argv[1], "clear") == 0) { | |
195 | clearPci9054 (); | |
196 | return 0; | |
197 | } | |
198 | ||
47e26b1b | 199 | return cmd_usage(cmdtp); |
affae2bf WD |
200 | } |
201 | ||
0d498393 WD |
202 | U_BOOT_CMD( |
203 | pci9054, 3, 1, do_pci9054, | |
2fb2604d | 204 | "PLX PCI9054 EEPROM access", |
8bde7f77 | 205 | "pci9054 info - print EEPROM values\n" |
a89c33db | 206 | "pci9054 update - updates EEPROM with default values" |
8bde7f77 WD |
207 | ); |
208 | ||
affae2bf | 209 | /* ------------------------------------------------------------------------- */ |