[thirdparty/u-boot.git] / board / esd / du405 / du405.c

/*
 * (C) Copyright 2000, 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include "du405.h"
#include <asm/processor.h>
#include <asm/ppc4xx.h>
#include <asm/ppc4xx-i2c.h>
#include <command.h>

DECLARE_GLOBAL_DATA_PTR;

extern void lxt971_no_sleep(void);


#if 0
#define FPGA_DEBUG
#endif

#if 0
#define FPGA_DEBUG2
#endif

/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] = {
#include "fpgadata.c"
};

/*
 * include common fpga code (for esd boards)
 */
#include "../common/fpga.c"


int board_early_init_f (void)
{
	int index, len, i;
	int status;

#ifdef FPGA_DEBUG
	/* set up serial port with default baudrate */
	(void) get_clocks ();
	gd->baudrate = CONFIG_BAUDRATE;
	serial_init ();
	console_init_f ();
#endif

	/*
	 * Boot onboard FPGA
	 */
	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
	if (status != 0) {
		/* booting FPGA failed */
#ifndef FPGA_DEBUG
		/* set up serial port with default baudrate */
		(void) get_clocks ();
		gd->baudrate = CONFIG_BAUDRATE;
		serial_init ();
		console_init_f ();
#endif
		printf ("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf ("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i = 0; i < 4; i++) {
			len = fpgadata[index];
			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
			index += len + 3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i = 20; i > 0; i--) {
			printf ("Rebooting in %2d seconds \r", i);
			for (index = 0; index < 1000; index++)
				udelay (1000);
		}
		putc ('\n');
		do_reset (NULL, 0, 0, NULL);
	}

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
	 * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
	 * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	 */
	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
	mtdcr (UIC0PR, 0xFFFFFFB1);	/* set int polarities */
	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 100 us
	 */
	mtebc (EBC0_CFG, 0xb8400000);

	return 0;
}


int misc_init_r (void)
{
	unsigned long CPC0_CR0Reg;

	/*
	 * Setup UART1 handshaking: use CTS instead of DSR
	 */
	CPC0_CR0Reg = mfdcr(CPC0_CR0);
	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);

	return (0);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	int index;
	int len;
	char str[64];
	int i = getenv_f("serial#", str, sizeof (str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming DU405");
	} else {
		puts (str);
	}

	puts ("\nFPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i = 0; i < 4; i++) {
		len = fpgadata[index];
		printf ("%s ", &(fpgadata[index + 1]));
		index += len + 3;
	}

	putc ('\n');

	/*
	 * Reset external DUART via FPGA
	 */
	out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
	out_8((void *)FPGA_MODE_REG, 0x00); /* low again */

	return 0;
}

void reset_phy(void)
{
#if defined(CONFIG_LXT971_NO_SLEEP)

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();
#endif
}
Commit	Line	Data
153d511e WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
153d511e WD	6	*/
	7
	8	#include <common.h>
	9	#include "du405.h"
	10	#include <asm/processor.h>
b36df561 SR	11	#include <asm/ppc4xx.h>
b36df561 SR	12	#include <asm/ppc4xx-i2c.h>
153d511e	13	#include <command.h>
8bde7f77	14
d87080b7 WD	15	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	16
ab379df3	17	extern void lxt971_no_sleep(void);
153d511e	18
153d511e WD	19
	20	#if 0
	21	#define FPGA_DEBUG
	22	#endif
	23
	24	#if 0
	25	#define FPGA_DEBUG2
	26	#endif
	27
	28	/* fpga configuration data - generated by bin2cc */
	29	const unsigned char fpgadata[] = {
	30	#include "fpgadata.c"
	31	};
	32
	33	/*
	34	* include common fpga code (for esd boards)
	35	*/
	36	#include "../common/fpga.c"
	37
	38
c837dcb1	39	int board_early_init_f (void)
153d511e	40	{
153d511e WD	41	int index, len, i;
	42	int status;
	43
	44	#ifdef FPGA_DEBUG
	45	/* set up serial port with default baudrate */
	46	(void) get_clocks ();
	47	gd->baudrate = CONFIG_BAUDRATE;
	48	serial_init ();
	49	console_init_f ();
	50	#endif
	51
	52	/*
	53	* Boot onboard FPGA
	54	*/
	55	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
	56	if (status != 0) {
	57	/* booting FPGA failed */
	58	#ifndef FPGA_DEBUG
	59	/* set up serial port with default baudrate */
	60	(void) get_clocks ();
	61	gd->baudrate = CONFIG_BAUDRATE;
	62	serial_init ();
	63	console_init_f ();
	64	#endif
	65	printf ("\nFPGA: Booting failed ");
	66	switch (status) {
	67	case ERROR_FPGA_PRG_INIT_LOW:
	68	printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	69	break;
	70	case ERROR_FPGA_PRG_INIT_HIGH:
	71	printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	72	break;
	73	case ERROR_FPGA_PRG_DONE:
	74	printf ("(Timeout: DONE not high after programming FPGA)\n ");
	75	break;
	76	}
	77
	78	/* display infos on fpgaimage */
	79	index = 15;
	80	for (i = 0; i < 4; i++) {
	81	len = fpgadata[index];
	82	printf ("FPGA: %s\n", &(fpgadata[index + 1]));
	83	index += len + 3;
	84	}
	85	putc ('\n');
	86	/* delayed reboot */
	87	for (i = 20; i > 0; i--) {
	88	printf ("Rebooting in %2d seconds \r", i);
	89	for (index = 0; index < 1000; index++)
	90	udelay (1000);
	91	}
	92	putc ('\n');
	93	do_reset (NULL, 0, 0, NULL);
	94	}
	95
	96	/*
	97	* IRQ 0-15 405GP internally generated; active high; level sensitive
	98	* IRQ 16 405GP internally generated; active low; level sensitive
	99	* IRQ 17-24 RESERVED
	100	* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	101	* IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
	102	* IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
	103	* IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
	104	* IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
105	* IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
106	* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
107	*/
952e7760 SR	108	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
	109	mtdcr (UIC0ER, 0x00000000); /* disable all ints */
	110	mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
	111	mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */
	112	mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
	113	mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
	114	mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
153d511e WD	115
	116	/*
	117	* EBC Configuration Register: set ready timeout to 100 us
	118	*/
d1c3b275	119	mtebc (EBC0_CFG, 0xb8400000);
153d511e WD	120
	121	return 0;
	122	}
	123
	124
82f4c6ac SR	125	int misc_init_r (void)
82f4c6ac SR	126	{
d1c3b275	127	unsigned long CPC0_CR0Reg;
82f4c6ac SR	128
	129	/*
	130	* Setup UART1 handshaking: use CTS instead of DSR
	131	*/
d1c3b275 SR	132	CPC0_CR0Reg = mfdcr(CPC0_CR0);
d1c3b275 SR	133	mtdcr(CPC0_CR0, CPC0_CR0Reg \| 0x00001000);
82f4c6ac SR	134
	135	return (0);
	136	}
	137
	138
153d511e WD	139	/*
	140	* Check Board Identity:
	141	*/
153d511e WD	142	int checkboard (void)
	143	{
	144	int index;
	145	int len;
77ddac94	146	char str[64];
cdb74977	147	int i = getenv_f("serial#", str, sizeof (str));
153d511e WD	148
	149	puts ("Board: ");
	150
	151	if (i == -1) {
	152	puts ("### No HW ID - assuming DU405");
	153	} else {
	154	puts (str);
	155	}
	156
	157	puts ("\nFPGA: ");
	158
	159	/* display infos on fpgaimage */
	160	index = 15;
	161	for (i = 0; i < 4; i++) {
	162	len = fpgadata[index];
	163	printf ("%s ", &(fpgadata[index + 1]));
	164	index += len + 3;
	165	}
	166
	167	putc ('\n');
	168
	169	/*
	170	* Reset external DUART via FPGA
	171	*/
bb57ad4b MF	172	out_8((void )FPGA_MODE_REG, 0xff); / reset high active */
bb57ad4b MF	173	out_8((void )FPGA_MODE_REG, 0x00); / low again */
153d511e	174
09db8f4d MF	175	return 0;
	176	}
	177
	178	void reset_phy(void)
	179	{
	180	#if defined(CONFIG_LXT971_NO_SLEEP)
	181
ab379df3 SR	182	/*
	183	* Disable sleep mode in LXT971
	184	*/
	185	lxt971_no_sleep();
09db8f4d	186	#endif
153d511e	187	}