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Commit | Line | Data |
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809ac5e7 SR |
1 | /* |
2 | * (C) Copyright 2001-2004 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
809ac5e7 SR |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/processor.h> | |
049216f0 | 10 | #include <asm/io.h> |
809ac5e7 SR |
11 | #include <command.h> |
12 | #include <malloc.h> | |
3ffc0d61 | 13 | #include <sja1000.h> |
809ac5e7 | 14 | |
d87080b7 | 15 | DECLARE_GLOBAL_DATA_PTR; |
809ac5e7 SR |
16 | |
17 | extern void lxt971_no_sleep(void); | |
18 | ||
3ffc0d61 MF |
19 | /* |
20 | * generate a short spike on the CAN tx line | |
21 | * to bring the couplers in sync | |
22 | */ | |
23 | void init_coupler(u32 addr) | |
24 | { | |
25 | struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; | |
26 | ||
27 | /* reset */ | |
28 | out_8(&ctrl->cr, CR_RR); | |
29 | ||
30 | /* dominant */ | |
31 | out_8(&ctrl->btr0, 0x00); /* btr setup is required */ | |
32 | out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ | |
33 | out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | | |
34 | OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); | |
35 | out_8(&ctrl->cr, 0x00); | |
36 | ||
37 | /* delay */ | |
38 | in_8(&ctrl->cr); | |
39 | in_8(&ctrl->cr); | |
40 | in_8(&ctrl->cr); | |
41 | in_8(&ctrl->cr); | |
42 | ||
43 | /* reset */ | |
44 | out_8(&ctrl->cr, CR_RR); | |
45 | } | |
46 | ||
809ac5e7 SR |
47 | int board_early_init_f (void) |
48 | { | |
49 | /* | |
50 | * IRQ 0-15 405GP internally generated; active high; level sensitive | |
51 | * IRQ 16 405GP internally generated; active low; level sensitive | |
52 | * IRQ 17-24 RESERVED | |
53 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive | |
54 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive | |
55 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive | |
56 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive | |
57 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive | |
58 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive | |
59 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive | |
60 | */ | |
952e7760 SR |
61 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
62 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
63 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ | |
64 | mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
65 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ | |
66 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ | |
67 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
809ac5e7 SR |
68 | |
69 | /* | |
70 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us | |
71 | */ | |
d1c3b275 | 72 | mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
809ac5e7 SR |
73 | |
74 | /* | |
75 | * Reset CPLD via GPIO12 (CS3) pin | |
76 | */ | |
049216f0 MF |
77 | out_be32((void *)GPIO0_OR, |
78 | in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12)); | |
809ac5e7 | 79 | udelay(1000); /* wait 1ms */ |
049216f0 MF |
80 | out_be32((void *)GPIO0_OR, |
81 | in_be32((void *)GPIO0_OR) | (0x80000000 >> 12)); | |
809ac5e7 SR |
82 | udelay(1000); /* wait 1ms */ |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
809ac5e7 SR |
87 | int misc_init_r (void) |
88 | { | |
809ac5e7 SR |
89 | /* adjust flash start and offset */ |
90 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
91 | gd->bd->bi_flashoffset = 0; | |
92 | ||
3ffc0d61 MF |
93 | /* |
94 | * Init magnetic coupler | |
95 | */ | |
96 | if (!getenv("noinitcoupler")) | |
97 | init_coupler(CAN_BA); | |
98 | ||
809ac5e7 SR |
99 | return (0); |
100 | } | |
101 | ||
809ac5e7 SR |
102 | /* |
103 | * Check Board Identity: | |
104 | */ | |
809ac5e7 SR |
105 | int checkboard (void) |
106 | { | |
18c5e64c | 107 | char str[64]; |
cdb74977 | 108 | int i = getenv_f("serial#", str, sizeof(str)); |
809ac5e7 SR |
109 | int flashcnt; |
110 | int delay; | |
049216f0 | 111 | u8 *led_reg = (u8 *)(CAN_BA + 0x1000); |
809ac5e7 SR |
112 | |
113 | puts ("Board: "); | |
114 | ||
115 | if (i == -1) { | |
116 | puts ("### No HW ID - assuming VOM405"); | |
117 | } else { | |
118 | puts(str); | |
119 | } | |
120 | ||
049216f0 | 121 | printf(" (PLD-Version=%02d)\n", in_8(led_reg)); |
809ac5e7 SR |
122 | |
123 | /* | |
124 | * Flash LEDs | |
125 | */ | |
126 | for (flashcnt = 0; flashcnt < 3; flashcnt++) { | |
049216f0 | 127 | out_8(led_reg, 0x40); /* LED_B..D off */ |
809ac5e7 SR |
128 | for (delay = 0; delay < 100; delay++) |
129 | udelay(1000); | |
049216f0 | 130 | out_8(led_reg, 0x47); /* LED_B..D on */ |
809ac5e7 SR |
131 | for (delay = 0; delay < 50; delay++) |
132 | udelay(1000); | |
133 | } | |
049216f0 | 134 | out_8(led_reg, 0x40); |
809ac5e7 | 135 | |
809ac5e7 SR |
136 | return 0; |
137 | } | |
138 | ||
feaedfcf | 139 | void reset_phy(void) |
809ac5e7 | 140 | { |
feaedfcf | 141 | #ifdef CONFIG_LXT971_NO_SLEEP |
809ac5e7 | 142 | |
feaedfcf SR |
143 | /* |
144 | * Disable sleep mode in LXT971 | |
145 | */ | |
146 | lxt971_no_sleep(); | |
147 | #endif | |
809ac5e7 | 148 | } |