]> git.ipfire.org Git - thirdparty/u-boot.git/blame - board/esd/wuh405/wuh405.c
Add GPL-2.0+ SPDX-License-Identifier to source files
[thirdparty/u-boot.git] / board / esd / wuh405 / wuh405.c
CommitLineData
6cfb1f0d
SR
1/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
6cfb1f0d
SR
6 */
7
8#include <common.h>
9#include <asm/processor.h>
10#include <command.h>
11#include <malloc.h>
12
13/* ------------------------------------------------------------------------- */
14
15#if 0
16#define FPGA_DEBUG
17#endif
18
6cfb1f0d
SR
19/* fpga configuration data - gzip compressed and generated by bin2c */
20const unsigned char fpgadata[] =
21{
22#include "fpgadata.c"
23};
24
25/*
26 * include common fpga code (for esd boards)
27 */
28#include "../common/fpga.c"
29
30
6cfb1f0d
SR
31int board_early_init_f (void)
32{
33 /*
34 * IRQ 0-15 405GP internally generated; active high; level sensitive
35 * IRQ 16 405GP internally generated; active low; level sensitive
36 * IRQ 17-24 RESERVED
37 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
38 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
39 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
40 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
41 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
42 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
43 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
44 */
952e7760
SR
45 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
46 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
47 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
48 mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
49 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
50 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
51 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
6cfb1f0d
SR
52
53 /*
54 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
55 */
d1c3b275 56 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
6cfb1f0d
SR
57
58 return 0;
59}
60
6cfb1f0d
SR
61int misc_init_r (void)
62{
6cfb1f0d
SR
63 unsigned char *dst;
64 ulong len = sizeof(fpgadata);
65 int status;
66 int index;
67 int i;
68
6d0f6bcf
JCPV
69 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
70 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
6cfb1f0d
SR
71 printf ("GUNZIP ERROR - must RESET board to recover\n");
72 do_reset (NULL, 0, 0, NULL);
73 }
74
75 status = fpga_boot(dst, len);
76 if (status != 0) {
77 printf("\nFPGA: Booting failed ");
78 switch (status) {
79 case ERROR_FPGA_PRG_INIT_LOW:
80 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
81 break;
82 case ERROR_FPGA_PRG_INIT_HIGH:
83 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
84 break;
85 case ERROR_FPGA_PRG_DONE:
86 printf("(Timeout: DONE not high after programming FPGA)\n ");
87 break;
88 }
89
90 /* display infos on fpgaimage */
91 index = 15;
92 for (i=0; i<4; i++) {
93 len = dst[index];
94 printf("FPGA: %s\n", &(dst[index+1]));
95 index += len+3;
96 }
97 putc ('\n');
98 /* delayed reboot */
99 for (i=20; i>0; i--) {
100 printf("Rebooting in %2d seconds \r",i);
101 for (index=0;index<1000;index++)
102 udelay(1000);
103 }
104 putc ('\n');
105 do_reset(NULL, 0, 0, NULL);
106 }
107
108 puts("FPGA: ");
109
110 /* display infos on fpgaimage */
111 index = 15;
112 for (i=0; i<4; i++) {
113 len = dst[index];
114 printf("%s ", &(dst[index+1]));
115 index += len+3;
116 }
117 putc ('\n');
118
119 free(dst);
120
121 /*
122 * Reset FPGA via FPGA_DATA pin
123 */
124 SET_FPGA(FPGA_PRG | FPGA_CLK);
125 udelay(1000); /* wait 1ms */
126 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
127 udelay(1000); /* wait 1ms */
128
129 /*
130 * Reset external DUARTs
131 */
049216f0
MF
132 out_be32((void *)GPIO0_OR,
133 in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
6cfb1f0d 134 udelay(10); /* wait 10us */
049216f0
MF
135 out_be32((void *)GPIO0_OR,
136 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
6cfb1f0d
SR
137 udelay(1000); /* wait 1ms */
138
6cfb1f0d
SR
139 /*
140 * Enable interrupts in exar duart mcr[3]
141 */
049216f0
MF
142 out_8((void *)(DUART0_BA + 4), 0x08);
143 out_8((void *)(DUART1_BA + 4), 0x08);
144 out_8((void *)(DUART2_BA + 4), 0x08);
145 out_8((void *)(DUART3_BA + 4), 0x08);
6cfb1f0d
SR
146
147 return (0);
148}
149
150
151/*
152 * Check Board Identity:
153 */
154
155int checkboard (void)
156{
77ddac94 157 char str[64];
cdb74977 158 int i = getenv_f("serial#", str, sizeof(str));
6cfb1f0d
SR
159
160 puts ("Board: ");
161
162 if (i == -1) {
163 puts ("### No HW ID - assuming WUH405");
164 } else {
165 puts(str);
166 }
167
168 putc ('\n');
169
170 return 0;
171}