[thirdparty/u-boot.git] / board / esteem192e / esteem192e.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Modified By Conn Clark to work with Esteem 192E 7/31/00
 */

#include <common.h>
#include <mpc8xx.h>

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 *
	 * active, NOP, read, precharge, NOP */
	0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
	0x11FFCC05,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 * NOP, Program
	 */
	0x0F0A8C34, 0x1F354C37,	/* last */

	_NOT_USED_,		/* Not used */

	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
	0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
	0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 * active, NOP, write, NOP, precharge, NOP */
	0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
	0x0FF74C04, 0x1FFFCC05,	/* last */
	_NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
	0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
	0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 * precharge, NOP, auto_ref, NOP, NOP, NOP */
	0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
	0x0FFFCCB4, 0x1FFFCC35,	/* last */
	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x0FFB8C00, 0x1FF74C03,	/* last */
	_NOT_USED_, _NOT_USED_
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	puts ("Board: Esteem 192E\n");
	return (0);
}

/* ------------------------------------------------------------------------- */


phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size_b0, size_b1;

	/*
	 * Explain frequency of refresh here
	 */

	memctl->memc_mptpr = 0x0200;	/* divide by 32 */

	memctl->memc_mamr = 0x18003112;	/*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */

	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	/* not defined yet */
	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;

	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;


	/* perform SDRAM initializsation sequence */
	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 0 execute 8 refresh */
	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */

	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 1 execute 8 refresh */
	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */

	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* 0x18803112  start refresh timer TODO: explain here */

/* printf ("banks 0 and 1 are programed\n"); */

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 */
	size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
	size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);

/* printf ("bank 1 size %u\n",size_b1); */

	if (size_b1 == 0) {
		/*
		 * Adjust refresh rate if bank 0 isn't stuffed
		 */
		memctl->memc_mptpr = 0x0400;	/* divide by 64 */
		memctl->memc_br3 &= 0x0FFFFFFFE;

		/*
		 * Adjust OR2 for size of bank 0
		 */
		memctl->memc_or2 |= 7 * size_b0;
	} else {
		if (size_b0 < size_b1) {
			memctl->memc_br2 &= 0x00007FFE;
			memctl->memc_br3 &= 0x00007FFF;

			/*
			 * Adjust OR3 for size of bank 1
			 */
			memctl->memc_or3 |= 15 * size_b1;

			/*
			 * Adjust OR2 for size of bank 0
			 */
			memctl->memc_or2 |= 15 * size_b0;
			memctl->memc_br2 += (size_b1 + 1);
		} else {
			memctl->memc_br3 &= 0x00007FFE;

			/*
			 * Adjust OR2 for size of bank 0
			 */
			memctl->memc_or2 |= 15 * size_b0;

			/*
			 * Adjust OR3 for size of bank 1
			 */
			memctl->memc_or3 |= 15 * size_b1;
			memctl->memc_br3 += (size_b0 + 1);
		}
	}

	/* before leaving set all unused i/o pins to outputs */

	/*
	 *      --*Unused Pin List*--
	 *
	 * group/port           bit number
	 * IP_B                 0,1,3,4,5  Taken care of in pcmcia-cs-x.x.xx
	 * PA                   5,7,8,9,14,15
	 * PB                   22,23,31
	 * PC                   4,5,6,7,10,11,12,13,14,15
	 * PD                   5,6,7
	 *
	 */

	/*
	 *   --*Pin Used for I/O List*--
	 *
	 * port     input bit number    output bit number    either
	 * PB                           18,26,27
	 * PD       3,4                                      8,9,10,11,12,13,14,15
	 *
	 */

	immap->im_ioport.iop_papar &= ~0x05C3;	/* set pins as io */
	immap->im_ioport.iop_padir |= 0x05C3;	/* set pins as output */
	immap->im_ioport.iop_paodr &= 0x0008;	/* config pins 9 & 14 as normal outputs */
	immap->im_ioport.iop_padat |= 0x05C3;	/* set unused pins as high */

	immap->im_cpm.cp_pbpar &= ~0x00001331;	/* set unused port b pins as io */
	immap->im_cpm.cp_pbdir |= 0x00001331;	/* set unused port b pins as output */
	immap->im_cpm.cp_pbodr &= ~0x00001331;	/* config bits 18,22,23,26,27 & 31 as normal outputs */
	immap->im_cpm.cp_pbdat |= 0x00001331;	/* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */

	immap->im_ioport.iop_pcpar &= ~0x0F3F;	/* set unused port c pins as io */
	immap->im_ioport.iop_pcdir |= 0x0F3F;	/* set unused port c pins as output */
	immap->im_ioport.iop_pcso &= ~0x0F3F;	/* clear special purpose bit for unused port c pins for clarity */
	immap->im_ioport.iop_pcdat |= 0x0F3F;	/* set unused port c pins high */

	immap->im_ioport.iop_pdpar &= 0xE000;	/* set pins as io */
	immap->im_ioport.iop_pddir &= 0xE000;	/* set bit 3 & 4 as inputs */
	immap->im_ioport.iop_pddir |= 0x07FF;	/* set bits 5 - 15 as outputs */
	immap->im_ioport.iop_pddat = 0x0055;	/* set alternating pattern on test port */

	return (size_b0 + size_b1);
}
Commit	Line	Data
16f21704 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
16f21704 WD	6	*
16f21704 WD	7	* Modified By Conn Clark to work with Esteem 192E 7/31/00
16f21704 WD	8	*/
	9
	10	#include <common.h>
	11	#include <mpc8xx.h>
	12
	13	/* ------------------------------------------------------------------------- */
	14
16f21704 WD	15	#define _NOT_USED_ 0xFFFFFFFF
16f21704 WD	16
c83bf6a2	17	const uint sdram_table[] = {
16f21704 WD	18	/*
	19	* Single Read. (Offset 0 in UPMA RAM)
	20	*
	21	* active, NOP, read, precharge, NOP */
	22	0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
c83bf6a2	23	0x11FFCC05, /* last */
16f21704 WD	24	/*
	25	* SDRAM Initialization (offset 5 in UPMA RAM)
	26	*
8bde7f77 WD	27	* This is no UPM entry point. The following definition uses
	28	* the remaining space to establish an initialization
	29	* sequence, which is executed by a RUN command.
16f21704 WD	30	* NOP, Program
16f21704 WD	31	*/
c83bf6a2	32	0x0F0A8C34, 0x1F354C37, /* last */
16f21704	33
c83bf6a2	34	_NOT_USED_, /* Not used */
16f21704 WD	35
	36	/*
	37	* Burst Read. (Offset 8 in UPMA RAM)
	38	* active, NOP, read, NOP, NOP, NOP, NOP, NOP */
	39	0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
c83bf6a2	40	0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
16f21704 WD	41	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	42	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	43	/*
	44	* Single Write. (Offset 18 in UPMA RAM)
	45	* active, NOP, write, NOP, precharge, NOP */
	46	0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
c83bf6a2	47	0x0FF74C04, 0x1FFFCC05, /* last */
16f21704 WD	48	_NOT_USED_, _NOT_USED_,
	49	/*
	50	* Burst Write. (Offset 20 in UPMA RAM)
	51	* active, NOP, write, NOP, NOP, NOP, NOP, NOP */
	52	0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
c83bf6a2	53	0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
16f21704 WD	54	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	55	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	56	/*
	57	* Refresh (Offset 30 in UPMA RAM)
	58	* precharge, NOP, auto_ref, NOP, NOP, NOP */
	59	0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
c83bf6a2 WD	60	0x0FFFCCB4, 0x1FFFCC35, /* last */
c83bf6a2 WD	61	_NOT_USED_, _NOT_USED_,
16f21704 WD	62	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	63	/*
	64	* Exception. (Offset 3c in UPMA RAM)
	65	*/
c83bf6a2 WD	66	0x0FFB8C00, 0x1FF74C03, /* last */
c83bf6a2 WD	67	_NOT_USED_, _NOT_USED_
16f21704 WD	68	};
	69
	70	/* ------------------------------------------------------------------------- */
	71
	72
	73	/*
	74	* Check Board Identity:
	75	*/
	76
	77	int checkboard (void)
	78	{
c83bf6a2 WD	79	puts ("Board: Esteem 192E\n");
c83bf6a2 WD	80	return (0);
16f21704 WD	81	}
	82
	83	/* ------------------------------------------------------------------------- */
	84
	85
9973e3c6	86	phys_size_t initdram (int board_type)
16f21704	87	{
6d0f6bcf	88	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	89	volatile memctl8xx_t *memctl = &immap->im_memctl;
c83bf6a2 WD	90	long int size_b0, size_b1;
16f21704	91
c83bf6a2 WD	92	/*
	93	* Explain frequency of refresh here
	94	*/
16f21704	95
c83bf6a2	96	memctl->memc_mptpr = 0x0200; /* divide by 32 */
16f21704	97
6d0f6bcf	98	memctl->memc_mamr = 0x18003112; /CONFIG_SYS_MAMR_8COL; / /* 0x18005112 TODO: explain here */
16f21704	99
c83bf6a2 WD	100	upmconfig (UPMA, (uint *) sdram_table,
c83bf6a2 WD	101	sizeof (sdram_table) / sizeof (uint));
16f21704	102
c83bf6a2 WD	103	/*
	104	* Map cs 2 and 3 to the SDRAM banks 0 and 1 at
	105	* preliminary addresses - these have to be modified after the
	106	* SDRAM size has been determined.
	107	*/
16f21704	108
6d0f6bcf JCPV	109	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */
6d0f6bcf JCPV	110	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
16f21704	111
6d0f6bcf JCPV	112	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
6d0f6bcf JCPV	113	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
16f21704	114
16f21704	115
c83bf6a2 WD	116	/* perform SDRAM initializsation sequence */
	117	memctl->memc_mar = 0x00000088;
	118	memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
	119	memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
16f21704	120
c83bf6a2 WD	121	memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
c83bf6a2 WD	122	memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
16f21704	123
6d0f6bcf	124	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
16f21704 WD	125
	126	/* printf ("banks 0 and 1 are programed\n"); */
	127
c83bf6a2 WD	128	/*
	129	* Check Bank 0 Memory Size for re-configuration
	130	*
	131	*/
77ddac94 WD	132	size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
77ddac94 WD	133	size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
16f21704	134
c83bf6a2	135	printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
16f21704 WD	136
	137	/* printf ("bank 1 size %u\n",size_b1); */
	138
c83bf6a2 WD	139	if (size_b1 == 0) {
	140	/*
	141	* Adjust refresh rate if bank 0 isn't stuffed
	142	*/
	143	memctl->memc_mptpr = 0x0400; /* divide by 64 */
	144	memctl->memc_br3 &= 0x0FFFFFFFE;
	145
	146	/*
	147	* Adjust OR2 for size of bank 0
	148	*/
	149	memctl->memc_or2 \|= 7 * size_b0;
	150	} else {
	151	if (size_b0 < size_b1) {
	152	memctl->memc_br2 &= 0x00007FFE;
	153	memctl->memc_br3 &= 0x00007FFF;
	154
	155	/*
	156	* Adjust OR3 for size of bank 1
	157	*/
	158	memctl->memc_or3 \|= 15 * size_b1;
	159
	160	/*
	161	* Adjust OR2 for size of bank 0
	162	*/
	163	memctl->memc_or2 \|= 15 * size_b0;
	164	memctl->memc_br2 += (size_b1 + 1);
	165	} else {
	166	memctl->memc_br3 &= 0x00007FFE;
	167
	168	/*
	169	* Adjust OR2 for size of bank 0
	170	*/
	171	memctl->memc_or2 \|= 15 * size_b0;
	172
	173	/*
	174	* Adjust OR3 for size of bank 1
	175	*/
	176	memctl->memc_or3 \|= 15 * size_b1;
	177	memctl->memc_br3 += (size_b0 + 1);
	178	}
	179	}
16f21704	180
c83bf6a2	181	/* before leaving set all unused i/o pins to outputs */
16f21704	182
c83bf6a2 WD	183	/*
	184	* --Unused Pin List--
	185	*
	186	* group/port bit number
	187	* IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
	188	* PA 5,7,8,9,14,15
	189	* PB 22,23,31
	190	* PC 4,5,6,7,10,11,12,13,14,15
	191	* PD 5,6,7
	192	*
	193	*/
16f21704	194
c83bf6a2 WD	195	/*
	196	* --Pin Used for I/O List--
	197	*
	198	* port input bit number output bit number either
	199	* PB 18,26,27
	200	* PD 3,4 8,9,10,11,12,13,14,15
	201	*
	202	*/
16f21704	203
c83bf6a2 WD	204	immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
	205	immap->im_ioport.iop_padir \|= 0x05C3; /* set pins as output */
	206	immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
	207	immap->im_ioport.iop_padat \|= 0x05C3; /* set unused pins as high */
16f21704	208
c83bf6a2 WD	209	immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
	210	immap->im_cpm.cp_pbdir \|= 0x00001331; /* set unused port b pins as output */
	211	immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
	212	immap->im_cpm.cp_pbdat \|= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
16f21704	213
c83bf6a2 WD	214	immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
	215	immap->im_ioport.iop_pcdir \|= 0x0F3F; /* set unused port c pins as output */
	216	immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
	217	immap->im_ioport.iop_pcdat \|= 0x0F3F; /* set unused port c pins high */
16f21704	218
c83bf6a2 WD	219	immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
	220	immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
	221	immap->im_ioport.iop_pddir \|= 0x07FF; /* set bits 5 - 15 as outputs */
	222	immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
16f21704	223
c83bf6a2	224	return (size_b0 + size_b1);
16f21704	225	}