[people/ms/u-boot.git] / board / esteem192e / esteem192e.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 *
 * Modified By Conn Clark to work with Esteem 192E 7/31/00
 *
 */

#include <common.h>
#include <mpc8xx.h>

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 *
	 * active, NOP, read, precharge, NOP */
	0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
	0x11FFCC05,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 * NOP, Program
	 */
	0x0F0A8C34, 0x1F354C37,	/* last */

	_NOT_USED_,		/* Not used */

	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
	0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
	0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 * active, NOP, write, NOP, precharge, NOP */
	0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
	0x0FF74C04, 0x1FFFCC05,	/* last */
	_NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
	0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
	0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 * precharge, NOP, auto_ref, NOP, NOP, NOP */
	0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
	0x0FFFCCB4, 0x1FFFCC35,	/* last */
	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x0FFB8C00, 0x1FF74C03,	/* last */
	_NOT_USED_, _NOT_USED_
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	puts ("Board: Esteem 192E\n");
	return (0);
}

/* ------------------------------------------------------------------------- */


phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size_b0, size_b1;

	/*
	 * Explain frequency of refresh here
	 */

	memctl->memc_mptpr = 0x0200;	/* divide by 32 */

	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */

	memctl->memc_or2 = CFG_OR2_PRELIM;	/* not defined yet */
	memctl->memc_br2 = CFG_BR2_PRELIM;

	memctl->memc_or3 = CFG_OR3_PRELIM;
	memctl->memc_br3 = CFG_BR3_PRELIM;


	/* perform SDRAM initializsation sequence */
	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 0 execute 8 refresh */
	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */

	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 1 execute 8 refresh */
	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */

	memctl->memc_mamr = CFG_MAMR_8COL;	/* 0x18803112  start refresh timer TODO: explain here */

/* printf ("banks 0 and 1 are programed\n"); */

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 */
	size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
	size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);

/* printf ("bank 1 size %u\n",size_b1); */

	if (size_b1 == 0) {
		/*
		 * Adjust refresh rate if bank 0 isn't stuffed
		 */
		memctl->memc_mptpr = 0x0400;	/* divide by 64 */
		memctl->memc_br3 &= 0x0FFFFFFFE;

		/*
		 * Adjust OR2 for size of bank 0
		 */
		memctl->memc_or2 |= 7 * size_b0;
	} else {
		if (size_b0 < size_b1) {
			memctl->memc_br2 &= 0x00007FFE;
			memctl->memc_br3 &= 0x00007FFF;

			/*
			 * Adjust OR3 for size of bank 1
			 */
			memctl->memc_or3 |= 15 * size_b1;

			/*
			 * Adjust OR2 for size of bank 0
			 */
			memctl->memc_or2 |= 15 * size_b0;
			memctl->memc_br2 += (size_b1 + 1);
		} else {
			memctl->memc_br3 &= 0x00007FFE;

			/*
			 * Adjust OR2 for size of bank 0
			 */
			memctl->memc_or2 |= 15 * size_b0;

			/*
			 * Adjust OR3 for size of bank 1
			 */
			memctl->memc_or3 |= 15 * size_b1;
			memctl->memc_br3 += (size_b0 + 1);
		}
	}

	/* before leaving set all unused i/o pins to outputs */

	/*
	 *      --*Unused Pin List*--
	 *
	 * group/port           bit number
	 * IP_B                 0,1,3,4,5  Taken care of in pcmcia-cs-x.x.xx
	 * PA                   5,7,8,9,14,15
	 * PB                   22,23,31
	 * PC                   4,5,6,7,10,11,12,13,14,15
	 * PD                   5,6,7
	 *
	 */

	/*
	 *   --*Pin Used for I/O List*--
	 *
	 * port     input bit number    output bit number    either
	 * PB                           18,26,27
	 * PD       3,4                                      8,9,10,11,12,13,14,15
	 *
	 */

	immap->im_ioport.iop_papar &= ~0x05C3;	/* set pins as io */
	immap->im_ioport.iop_padir |= 0x05C3;	/* set pins as output */
	immap->im_ioport.iop_paodr &= 0x0008;	/* config pins 9 & 14 as normal outputs */
	immap->im_ioport.iop_padat |= 0x05C3;	/* set unused pins as high */

	immap->im_cpm.cp_pbpar &= ~0x00001331;	/* set unused port b pins as io */
	immap->im_cpm.cp_pbdir |= 0x00001331;	/* set unused port b pins as output */
	immap->im_cpm.cp_pbodr &= ~0x00001331;	/* config bits 18,22,23,26,27 & 31 as normal outputs */
	immap->im_cpm.cp_pbdat |= 0x00001331;	/* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */

	immap->im_ioport.iop_pcpar &= ~0x0F3F;	/* set unused port c pins as io */
	immap->im_ioport.iop_pcdir |= 0x0F3F;	/* set unused port c pins as output */
	immap->im_ioport.iop_pcso &= ~0x0F3F;	/* clear special purpose bit for unused port c pins for clarity */
	immap->im_ioport.iop_pcdat |= 0x0F3F;	/* set unused port c pins high */

	immap->im_ioport.iop_pdpar &= 0xE000;	/* set pins as io */
	immap->im_ioport.iop_pddir &= 0xE000;	/* set bit 3 & 4 as inputs */
	immap->im_ioport.iop_pddir |= 0x07FF;	/* set bits 5 - 15 as outputs */
	immap->im_ioport.iop_pddat = 0x0055;	/* set alternating pattern on test port */

	return (size_b0 + size_b1);
}
Commit	Line	Data
16f21704 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*
	24	* Modified By Conn Clark to work with Esteem 192E 7/31/00
	25	*
	26	*/
	27
	28	#include <common.h>
	29	#include <mpc8xx.h>
	30
	31	/* ------------------------------------------------------------------------- */
	32
16f21704 WD	33	#define _NOT_USED_ 0xFFFFFFFF
16f21704 WD	34
c83bf6a2	35	const uint sdram_table[] = {
16f21704 WD	36	/*
	37	* Single Read. (Offset 0 in UPMA RAM)
	38	*
	39	* active, NOP, read, precharge, NOP */
	40	0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
c83bf6a2	41	0x11FFCC05, /* last */
16f21704 WD	42	/*
	43	* SDRAM Initialization (offset 5 in UPMA RAM)
	44	*
8bde7f77 WD	45	* This is no UPM entry point. The following definition uses
	46	* the remaining space to establish an initialization
	47	* sequence, which is executed by a RUN command.
16f21704 WD	48	* NOP, Program
16f21704 WD	49	*/
c83bf6a2	50	0x0F0A8C34, 0x1F354C37, /* last */
16f21704	51
c83bf6a2	52	_NOT_USED_, /* Not used */
16f21704 WD	53
	54	/*
	55	* Burst Read. (Offset 8 in UPMA RAM)
	56	* active, NOP, read, NOP, NOP, NOP, NOP, NOP */
	57	0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
c83bf6a2	58	0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
16f21704 WD	59	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	60	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	61	/*
	62	* Single Write. (Offset 18 in UPMA RAM)
	63	* active, NOP, write, NOP, precharge, NOP */
	64	0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
c83bf6a2	65	0x0FF74C04, 0x1FFFCC05, /* last */
16f21704 WD	66	_NOT_USED_, _NOT_USED_,
	67	/*
	68	* Burst Write. (Offset 20 in UPMA RAM)
	69	* active, NOP, write, NOP, NOP, NOP, NOP, NOP */
	70	0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
c83bf6a2	71	0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
16f21704 WD	72	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	73	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	74	/*
	75	* Refresh (Offset 30 in UPMA RAM)
	76	* precharge, NOP, auto_ref, NOP, NOP, NOP */
	77	0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
c83bf6a2 WD	78	0x0FFFCCB4, 0x1FFFCC35, /* last */
c83bf6a2 WD	79	_NOT_USED_, _NOT_USED_,
16f21704 WD	80	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	81	/*
	82	* Exception. (Offset 3c in UPMA RAM)
	83	*/
c83bf6a2 WD	84	0x0FFB8C00, 0x1FF74C03, /* last */
c83bf6a2 WD	85	_NOT_USED_, _NOT_USED_
16f21704 WD	86	};
	87
	88	/* ------------------------------------------------------------------------- */
	89
	90
	91	/*
	92	* Check Board Identity:
	93	*/
	94
	95	int checkboard (void)
	96	{
c83bf6a2 WD	97	puts ("Board: Esteem 192E\n");
c83bf6a2 WD	98	return (0);
16f21704 WD	99	}
	100
	101	/* ------------------------------------------------------------------------- */
	102
	103
9973e3c6	104	phys_size_t initdram (int board_type)
16f21704	105	{
c83bf6a2 WD	106	volatile immap_t immap = (immap_t ) CFG_IMMR;
	107	volatile memctl8xx_t *memctl = &immap->im_memctl;
	108	long int size_b0, size_b1;
16f21704	109
c83bf6a2 WD	110	/*
	111	* Explain frequency of refresh here
	112	*/
16f21704	113
c83bf6a2	114	memctl->memc_mptpr = 0x0200; /* divide by 32 */
16f21704	115
cd37d9e6	116	memctl->memc_mamr = 0x18003112; /CFG_MAMR_8COL; / /* 0x18005112 TODO: explain here */
16f21704	117
c83bf6a2 WD	118	upmconfig (UPMA, (uint *) sdram_table,
c83bf6a2 WD	119	sizeof (sdram_table) / sizeof (uint));
16f21704	120
c83bf6a2 WD	121	/*
	122	* Map cs 2 and 3 to the SDRAM banks 0 and 1 at
	123	* preliminary addresses - these have to be modified after the
	124	* SDRAM size has been determined.
	125	*/
16f21704	126
c83bf6a2 WD	127	memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */
c83bf6a2 WD	128	memctl->memc_br2 = CFG_BR2_PRELIM;
16f21704	129
c83bf6a2 WD	130	memctl->memc_or3 = CFG_OR3_PRELIM;
c83bf6a2 WD	131	memctl->memc_br3 = CFG_BR3_PRELIM;
16f21704	132
16f21704	133
c83bf6a2 WD	134	/* perform SDRAM initializsation sequence */
	135	memctl->memc_mar = 0x00000088;
	136	memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
	137	memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
16f21704	138
c83bf6a2 WD	139	memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
c83bf6a2 WD	140	memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
16f21704	141
c83bf6a2	142	memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
16f21704 WD	143
	144	/* printf ("banks 0 and 1 are programed\n"); */
	145
c83bf6a2 WD	146	/*
	147	* Check Bank 0 Memory Size for re-configuration
	148	*
	149	*/
77ddac94 WD	150	size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
77ddac94 WD	151	size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
16f21704	152
c83bf6a2	153	printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
16f21704 WD	154
	155	/* printf ("bank 1 size %u\n",size_b1); */
	156
c83bf6a2 WD	157	if (size_b1 == 0) {
	158	/*
	159	* Adjust refresh rate if bank 0 isn't stuffed
	160	*/
	161	memctl->memc_mptpr = 0x0400; /* divide by 64 */
	162	memctl->memc_br3 &= 0x0FFFFFFFE;
	163
	164	/*
	165	* Adjust OR2 for size of bank 0
	166	*/
	167	memctl->memc_or2 \|= 7 * size_b0;
	168	} else {
	169	if (size_b0 < size_b1) {
	170	memctl->memc_br2 &= 0x00007FFE;
	171	memctl->memc_br3 &= 0x00007FFF;
	172
	173	/*
	174	* Adjust OR3 for size of bank 1
	175	*/
	176	memctl->memc_or3 \|= 15 * size_b1;
	177
	178	/*
	179	* Adjust OR2 for size of bank 0
	180	*/
	181	memctl->memc_or2 \|= 15 * size_b0;
	182	memctl->memc_br2 += (size_b1 + 1);
	183	} else {
	184	memctl->memc_br3 &= 0x00007FFE;
	185
	186	/*
	187	* Adjust OR2 for size of bank 0
	188	*/
	189	memctl->memc_or2 \|= 15 * size_b0;
	190
	191	/*
	192	* Adjust OR3 for size of bank 1
	193	*/
	194	memctl->memc_or3 \|= 15 * size_b1;
	195	memctl->memc_br3 += (size_b0 + 1);
	196	}
	197	}
16f21704	198
c83bf6a2	199	/* before leaving set all unused i/o pins to outputs */
16f21704	200
c83bf6a2 WD	201	/*
	202	* --Unused Pin List--
	203	*
	204	* group/port bit number
	205	* IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
	206	* PA 5,7,8,9,14,15
	207	* PB 22,23,31
	208	* PC 4,5,6,7,10,11,12,13,14,15
	209	* PD 5,6,7
	210	*
	211	*/
16f21704	212
c83bf6a2 WD	213	/*
	214	* --Pin Used for I/O List--
	215	*
	216	* port input bit number output bit number either
	217	* PB 18,26,27
	218	* PD 3,4 8,9,10,11,12,13,14,15
	219	*
	220	*/
16f21704	221
c83bf6a2 WD	222	immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
	223	immap->im_ioport.iop_padir \|= 0x05C3; /* set pins as output */
	224	immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
	225	immap->im_ioport.iop_padat \|= 0x05C3; /* set unused pins as high */
16f21704	226
c83bf6a2 WD	227	immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
	228	immap->im_cpm.cp_pbdir \|= 0x00001331; /* set unused port b pins as output */
	229	immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
	230	immap->im_cpm.cp_pbdat \|= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
16f21704	231
c83bf6a2 WD	232	immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
	233	immap->im_ioport.iop_pcdir \|= 0x0F3F; /* set unused port c pins as output */
	234	immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
	235	immap->im_ioport.iop_pcdat \|= 0x0F3F; /* set unused port c pins high */
16f21704	236
c83bf6a2 WD	237	immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
	238	immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
	239	immap->im_ioport.iop_pddir \|= 0x07FF; /* set bits 5 - 15 as outputs */
	240	immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
16f21704	241
c83bf6a2	242	return (size_b0 + size_b1);
16f21704	243	}