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5772de44 WD |
1 | /************************************************************************** |
2 | Etherboot - BOOTP/TFTP Bootstrap Program | |
3 | Skeleton NIC driver for Etherboot | |
4 | ***************************************************************************/ | |
5 | ||
6 | /* | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2, or (at | |
10 | * your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file is a modified version from the Galileo polled mode | |
15 | * network driver for the ethernet contained within the GT64260 | |
16 | * chip. It has been modified to fit into the U-Boot framework, from | |
17 | * the original (etherboot) setup. Also, additional cleanup and features | |
18 | * were added. | |
19 | * | |
20 | * - Josh Huber <huber@mclx.com> | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <malloc.h> | |
5772de44 WD |
25 | #include <galileo/gt64260R.h> |
26 | #include <galileo/core.h> | |
27 | #include <asm/cache.h> | |
28 | #include <miiphy.h> | |
29 | #include <net.h> | |
30 | ||
31 | #include "eth.h" | |
32 | #include "eth_addrtbl.h" | |
33 | ||
b9307262 | 34 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) |
5772de44 WD |
35 | |
36 | #define GT6426x_ETH_BUF_SIZE 1536 | |
37 | ||
38 | /* if you like verbose output, turn this on! */ | |
39 | #undef DEBUG | |
40 | ||
41 | /* Restart autoneg if we detect link is up on phy init. */ | |
42 | ||
43 | /* | |
44 | * The GT doc's say that after Rst is deasserted, and the PHY | |
45 | * reports autoneg complete, it runs through its autoneg | |
46 | * procedures. This doesn't seem to be the case for MII | |
47 | * PHY's. To work around this check for link up && autoneg | |
48 | * complete when initilizing the port. If they are both set, | |
49 | * then restart PHY autoneg. Of course, it may be something | |
50 | * completly different. | |
51 | */ | |
52 | #ifdef CONFIG_ETHER_PORT_MII | |
53 | # define RESTART_AUTONEG | |
54 | #endif | |
55 | ||
56 | /* do this if you dont want to use snooping */ | |
57 | #define USE_SOFTWARE_CACHE_MANAGEMENT | |
58 | ||
59 | #ifdef USE_SOFTWARE_CACHE_MANAGEMENT | |
60 | #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} | |
61 | #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} | |
62 | #define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} | |
63 | #else | |
64 | /* bummer - w/o flush, nothing works, even with snooping - FIXME */ | |
65 | /* #define FLUSH_DCACHE(a,b) */ | |
66 | #define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} | |
67 | #define FLUSH_AND_INVALIDATE_DCACHE(a,b) | |
68 | #define INVALIDATE_DCACHE(a,b) | |
69 | #endif | |
70 | struct eth_dev_s { | |
71 | eth0_tx_desc_single *eth_tx_desc; | |
72 | eth0_rx_desc_single *eth_rx_desc; | |
73 | char *eth_tx_buffer; | |
74 | char *eth_rx_buffer[NR]; | |
75 | int tdn, rdn; | |
76 | int dev; | |
77 | unsigned int reg_base; | |
78 | }; | |
79 | ||
80 | ||
81 | #ifdef CONFIG_INTEL_LXT97X | |
82 | /* for intel LXT972 */ | |
83 | static const char ether_port_phy_addr[3]={0,1,2}; | |
84 | #else | |
85 | static const char ether_port_phy_addr[3]={4,5,6}; | |
86 | #endif | |
87 | ||
63ff004c MB |
88 | /* MII PHY access routines are common for all i/f, use gal_ent0 */ |
89 | #define GT6426x_MII_DEVNAME "gal_enet0" | |
90 | ||
91 | int gt6426x_miiphy_read(char *devname, unsigned char phy, | |
92 | unsigned char reg, unsigned short *val); | |
5772de44 WD |
93 | |
94 | static inline unsigned short | |
95 | miiphy_read_ret(unsigned short phy, unsigned short reg) | |
96 | { | |
97 | unsigned short val; | |
63ff004c | 98 | gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val); |
5772de44 WD |
99 | return val; |
100 | } | |
101 | ||
102 | ||
103 | /************************************************************************** | |
104 | RESET - Reset adapter | |
105 | ***************************************************************************/ | |
106 | void | |
107 | gt6426x_eth_reset(void *v) | |
108 | { | |
109 | /* we should do something here... | |
110 | struct eth_device *wp = (struct eth_device *)v; | |
111 | struct eth_dev_s *p = wp->priv; | |
112 | */ | |
113 | ||
114 | printf ("RESET\n"); | |
115 | /* put the card in its initial state */ | |
116 | } | |
117 | ||
118 | static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) | |
119 | { | |
120 | #ifdef DEBUG | |
121 | printf("SMI interrupt: "); | |
122 | ||
123 | if(icr&0x20000000) { | |
8bde7f77 | 124 | printf("SMI done\n"); |
5772de44 WD |
125 | } |
126 | #endif | |
127 | ||
128 | if(icr&0x10000000) { | |
8bde7f77 | 129 | unsigned int psr; |
5772de44 WD |
130 | psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); |
131 | #ifdef DEBUG | |
132 | printf("PHY state change:\n" | |
133 | " GT:%s:%s:%s:%s\n", | |
134 | psr&1?"100":" 10", | |
135 | psr&8?" Link":"nLink", | |
136 | psr&2?"FD":"HD", | |
137 | psr&4?" FC":"nFC"); | |
138 | ||
139 | #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ | |
140 | { | |
8bde7f77 | 141 | unsigned short mii_11; |
5772de44 WD |
142 | mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11); |
143 | ||
144 | printf(" mii:%s:%s:%s:%s %s:%s %s\n", | |
145 | mii_11&(1<<14)?"100":" 10", | |
146 | mii_11&(1<<10)?" Link":"nLink", | |
147 | mii_11&(1<<9)?"FD":"HD", | |
148 | mii_11&(1<<4)?" FC":"nFC", | |
149 | ||
150 | mii_11&(1<<7)?"ANc":"ANnc", | |
151 | mii_11&(1<<8)?"AN":"Manual", | |
152 | "" | |
153 | ); | |
154 | } | |
155 | #endif /* CONFIG_INTEL_LXT97X */ | |
156 | #endif /* DEBUG */ | |
157 | } | |
158 | } | |
159 | ||
160 | static int | |
161 | gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) | |
162 | { | |
163 | int eth_len=0; | |
164 | char *eth_data; | |
165 | ||
166 | eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)]; | |
167 | ||
168 | INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); | |
169 | ||
170 | if (rx->command_status & 0x80000000) { | |
171 | return 0; /* No packet received */ | |
172 | } | |
173 | ||
174 | eth_len = (unsigned int) | |
175 | (rx->buff_size_byte_count) & 0x0000ffff; | |
176 | eth_data = (char *) p->eth_rx_buffer[p->rdn]; | |
177 | ||
178 | #ifdef DEBUG | |
179 | if (eth_len) { | |
180 | printf ("%s: Recived %d byte Packet @ 0x%p\n", | |
181 | __FUNCTION__, eth_len, eth_data); | |
182 | } | |
183 | #endif | |
184 | /* | |
185 | * packet is now in: | |
186 | * eth0_rx_buffer[RDN_ETH0]; | |
187 | */ | |
188 | ||
189 | /* let the upper layer handle the packet */ | |
77ddac94 | 190 | NetReceive ((uchar *)eth_data, eth_len); |
5772de44 WD |
191 | |
192 | rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; | |
193 | ||
194 | ||
195 | /* GT96100 Owner */ | |
196 | rx->command_status = 0x80000000; | |
197 | ||
198 | FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); | |
199 | ||
200 | p->rdn ++; | |
201 | if (p->rdn == NR) {p->rdn = 0;} | |
202 | ||
203 | sync(); | |
204 | ||
205 | /* Start Rx*/ | |
206 | GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080); | |
207 | ||
208 | #ifdef DEBUG | |
209 | { | |
210 | int i; | |
211 | for (i=0;i<12;i++) { | |
212 | printf(" %02x", eth_data[i]); | |
213 | } | |
214 | } | |
215 | printf(": %d bytes\n", eth_len); | |
216 | #endif | |
217 | INVALIDATE_DCACHE((unsigned int)eth_data, | |
218 | (unsigned int)eth_data+eth_len); | |
219 | return eth_len; | |
220 | } | |
221 | ||
222 | /************************************************************************** | |
223 | POLL - look for an rx frame, handle other conditions | |
224 | ***************************************************************************/ | |
225 | int | |
226 | gt6426x_eth_poll(void *v) | |
227 | { | |
228 | struct eth_device *wp = (struct eth_device *)v; | |
229 | struct eth_dev_s *p = wp->priv; | |
230 | unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base); | |
231 | ||
232 | if(icr) { | |
233 | GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0); | |
234 | #ifdef DEBUG | |
235 | printf("poll got ICR %08x\n", icr); | |
236 | #endif | |
237 | /* SMI done or PHY state change*/ | |
238 | if(icr&0x30000000) gt6426x_handle_SMI(p, icr); | |
239 | } | |
240 | /* always process. We aren't using RX interrupts */ | |
241 | return gt6426x_eth_receive(p, icr); | |
242 | } | |
243 | ||
244 | /************************************************************************** | |
245 | TRANSMIT - Transmit a frame | |
246 | ***************************************************************************/ | |
247 | int | |
248 | gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s) | |
249 | { | |
250 | struct eth_device *wp = (struct eth_device *)v; | |
251 | struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv; | |
252 | #ifdef DEBUG | |
253 | unsigned int old_command_stat,old_psr; | |
254 | #endif | |
255 | eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn]; | |
256 | ||
257 | /* wait for tx to be ready */ | |
258 | INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); | |
259 | while (tx->command_status & 0x80000000) { | |
260 | int i; | |
261 | for(i=0;i<1000;i++); | |
262 | INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); | |
263 | } | |
264 | ||
265 | GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base, | |
266 | (unsigned int)tx); | |
267 | ||
268 | #ifdef DEBUG | |
269 | printf("copying to tx_buffer [%p], length %x, desc = %p\n", | |
270 | dev->eth_tx_buffer, s, dev->eth_tx_desc); | |
271 | #endif | |
272 | memcpy(dev->eth_tx_buffer, (char *) p, s); | |
273 | ||
77ddac94 | 274 | tx->buff_pointer = (uchar *)dev->eth_tx_buffer; |
5772de44 WD |
275 | tx->bytecount_reserved = ((__u16)s) << 16; |
276 | ||
277 | /* 31 - own | |
278 | * 22 - gencrc | |
279 | * 18:16 - pad, last, first */ | |
280 | tx->command_status = (1<<31) | (1<<22) | (7<<16); | |
281 | #if 0 | |
282 | /* FEr #18 */ | |
283 | tx->next_desc = NULL; | |
284 | #else | |
285 | tx->next_desc = | |
286 | (struct eth0_tx_desc_struct *) | |
287 | &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved; | |
288 | ||
289 | /* cpu owned */ | |
290 | dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */ | |
291 | #endif | |
292 | ||
293 | #ifdef DEBUG | |
294 | old_command_stat=tx->command_status, | |
295 | old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); | |
296 | #endif | |
297 | ||
298 | FLUSH_DCACHE((unsigned int)tx, | |
299 | (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]); | |
300 | ||
301 | FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s); | |
302 | ||
303 | GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000); | |
304 | ||
305 | #ifdef DEBUG | |
306 | { | |
307 | unsigned int command_stat=0; | |
308 | printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr); | |
309 | /* wait for tx to be ready */ | |
310 | do { | |
311 | unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base); | |
312 | command_stat=tx->command_status; | |
313 | if(command_stat!=old_command_stat || psr !=old_psr) { | |
314 | printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr); | |
315 | old_command_stat = command_stat; | |
316 | old_psr = psr; | |
317 | } | |
318 | /* gt6426x_eth0_poll(); */ | |
319 | } while (command_stat & 0x80000000); | |
320 | ||
321 | printf("sent %d byte frame\n", s); | |
322 | ||
323 | if((command_stat & (3<<15)) == 3) { | |
324 | printf("frame had error (stat=%08x)\n", command_stat); | |
325 | } | |
326 | } | |
327 | #endif | |
328 | return 0; | |
329 | } | |
330 | ||
331 | /************************************************************************** | |
332 | DISABLE - Turn off ethernet interface | |
333 | ***************************************************************************/ | |
334 | void | |
335 | gt6426x_eth_disable(void *v) | |
336 | { | |
337 | struct eth_device *wp = (struct eth_device *)v; | |
338 | struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; | |
339 | ||
340 | GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000); | |
341 | } | |
342 | ||
343 | /************************************************************************** | |
344 | MII utilities - write: write to an MII register via SMI | |
345 | ***************************************************************************/ | |
346 | int | |
63ff004c MB |
347 | gt6426x_miiphy_write(char *devname, unsigned char phy, |
348 | unsigned char reg, unsigned short data) | |
5772de44 WD |
349 | { |
350 | unsigned int temp= (reg<<21) | (phy<<16) | data; | |
351 | ||
352 | while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ | |
353 | ||
354 | GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); | |
355 | return 0; | |
356 | } | |
357 | ||
358 | /************************************************************************** | |
359 | MII utilities - read: read from an MII register via SMI | |
360 | ***************************************************************************/ | |
361 | int | |
63ff004c MB |
362 | gt6426x_miiphy_read(char *devname, unsigned char phy, |
363 | unsigned char reg, unsigned short *val) | |
5772de44 WD |
364 | { |
365 | unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; | |
366 | ||
367 | while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */ | |
368 | ||
369 | GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp); | |
370 | ||
371 | while(1) { | |
372 | temp=GTREGREAD(ETHERNET_SMI_REGISTER); | |
373 | if(temp & (1<<27)) break; /* wait for ReadValid */ | |
374 | } | |
375 | *val = temp & 0xffff; | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | #ifdef DEBUG | |
381 | /************************************************************************** | |
382 | MII utilities - dump mii registers | |
383 | ***************************************************************************/ | |
384 | static void | |
385 | gt6426x_dump_mii(bd_t *bis, unsigned short phy) | |
386 | { | |
387 | printf("mii reg 0 - 3: %04x %04x %04x %04x\n", | |
8bde7f77 | 388 | miiphy_read_ret(phy, 0x0), |
5772de44 WD |
389 | miiphy_read_ret(phy, 0x1), |
390 | miiphy_read_ret(phy, 0x2), | |
391 | miiphy_read_ret(phy, 0x3) | |
392 | ); | |
393 | printf(" 4 - 7: %04x %04x %04x %04x\n", | |
394 | miiphy_read_ret(phy, 0x4), | |
395 | miiphy_read_ret(phy, 0x5), | |
396 | miiphy_read_ret(phy, 0x6), | |
397 | miiphy_read_ret(phy, 0x7) | |
398 | ); | |
399 | printf(" 8: %04x\n", | |
400 | miiphy_read_ret(phy, 0x8) | |
401 | ); | |
402 | printf(" 16-19: %04x %04x %04x %04x\n", | |
403 | miiphy_read_ret(phy, 0x10), | |
404 | miiphy_read_ret(phy, 0x11), | |
405 | miiphy_read_ret(phy, 0x12), | |
406 | miiphy_read_ret(phy, 0x13) | |
407 | ); | |
408 | printf(" 20,30: %04x %04x\n", | |
409 | miiphy_read_ret(phy, 20), | |
410 | miiphy_read_ret(phy, 30) | |
411 | ); | |
412 | } | |
413 | #endif | |
414 | ||
415 | #ifdef RESTART_AUTONEG | |
416 | ||
417 | /* If link is up && autoneg compleate, and if | |
418 | * GT and PHY disagree about link capabilitys, | |
419 | * restart autoneg - something screwy with FD/HD | |
420 | * unless we do this. */ | |
421 | static void | |
422 | check_phy_state(struct eth_dev_s *p) | |
423 | { | |
424 | int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR); | |
425 | int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); | |
426 | ||
427 | if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { | |
428 | int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) & | |
429 | miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR); | |
430 | int want; | |
431 | ||
432 | if (nego & PHY_ANLPAR_TXFD) { | |
433 | want = 0x3; | |
434 | printf("MII: 100Base-TX, Full Duplex\n"); | |
435 | } else if (nego & PHY_ANLPAR_TX) { | |
436 | want = 0x1; | |
437 | printf("MII: 100Base-TX, Half Duplex\n"); | |
438 | } else if (nego & PHY_ANLPAR_10FD) { | |
439 | want = 0x2; | |
440 | printf("MII: 10Base-T, Full Duplex\n"); | |
441 | } else if (nego & PHY_ANLPAR_10) { | |
442 | want = 0x0; | |
443 | printf("MII: 10Base-T, Half Duplex\n"); | |
444 | } else { | |
445 | printf("MII: Unknown link-foo! %x\n", nego); | |
446 | return; | |
447 | } | |
448 | ||
449 | if ((psr & 0x3) != want) { | |
450 | printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n", | |
451 | psr & 0x3, want); | |
63ff004c | 452 | miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0, |
5772de44 WD |
453 | miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9)); |
454 | udelay(10000); /* the EVB's GT takes a while to notice phy | |
455 | went down and up */ | |
456 | } | |
457 | } | |
458 | } | |
459 | #endif | |
460 | ||
461 | /************************************************************************** | |
462 | PROBE - Look for an adapter, this routine's visible to the outside | |
463 | ***************************************************************************/ | |
464 | int | |
465 | gt6426x_eth_probe(void *v, bd_t *bis) | |
466 | { | |
467 | struct eth_device *wp = (struct eth_device *)v; | |
468 | struct eth_dev_s *p = (struct eth_dev_s *)wp->priv; | |
469 | int dev = p->dev; | |
470 | unsigned int reg_base = p->reg_base; | |
471 | unsigned long temp; | |
472 | int i; | |
473 | ||
474 | if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS )) | |
475 | { /* This should never happen */ | |
476 | printf("%s: Invalid device %d\n", __FUNCTION__, dev ); | |
477 | return 0; | |
478 | } | |
479 | ||
480 | #ifdef DEBUG | |
481 | printf ("%s: initializing %s\n", __FUNCTION__, wp->name ); | |
482 | printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n", | |
483 | GTREGREAD(COMM_UNIT_ARBITER_CONTROL), | |
484 | GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER)); | |
485 | #endif | |
486 | ||
487 | /* clear MIB counters */ | |
488 | for(i=0;i<255; i++) | |
489 | temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i); | |
490 | ||
491 | #ifdef CONFIG_INTEL_LXT97X | |
492 | /* for intel LXT972 */ | |
493 | ||
494 | /* led 1: 0x1=txact | |
495 | led 2: 0xc=link/rxact | |
496 | led 3: 0x2=rxact (N/C) | |
497 | strch: 0,2=30 ms, enable */ | |
63ff004c | 498 | miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22); |
5772de44 WD |
499 | |
500 | /* 2.7ns port rise time */ | |
501 | /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */ | |
502 | #else | |
503 | /* already set up in mpsc.c */ | |
504 | /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */ | |
505 | ||
506 | /* already set up in sdram_init.S... */ | |
507 | /* MPSC0, MPSC1, RMII */ | |
508 | /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */ | |
509 | #endif | |
510 | GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER, | |
511 | ether_port_phy_addr[0] | | |
512 | (ether_port_phy_addr[1]<<5) | | |
513 | (ether_port_phy_addr[2]<<10)); /* 2000 */ | |
514 | ||
515 | /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes) | |
516 | * 9 - 1: RIFB - interrupt on frame boundaries only | |
517 | * 6:7 - 00: big endian rx and tx | |
518 | * 5:2 - 1111: 15 retries */ | |
519 | GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base, | |
520 | (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */ | |
521 | ||
522 | #ifndef USE_SOFTWARE_CACHE_MANAGEMENT | |
523 | /* enable rx/tx desc/buffer cache snoop */ | |
524 | GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, | |
525 | &temp); /* f200 */ | |
526 | temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30); | |
527 | GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20, | |
528 | temp); | |
529 | #endif | |
530 | ||
531 | /* 31 28 27 24 23 20 19 16 | |
532 | * 0000 0000 0000 0000 [0004] | |
533 | * 15 12 11 8 7 4 3 0 | |
534 | * 1000 1101 0000 0000 [4d00] | |
535 | * 20 - 0=MII 1=RMII | |
536 | * 19 - 0=speed autoneg | |
537 | * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE) | |
538 | * 11 - no force link pass | |
539 | * 10 - 1=disable fctl autoneg | |
540 | * 8 - override prio ?? */ | |
541 | temp = 0x00004d00; | |
542 | #ifndef CONFIG_ETHER_PORT_MII | |
543 | temp |= (1<<20); /* RMII */ | |
544 | #endif | |
545 | /* set En */ | |
546 | GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base, | |
547 | temp); /* 2408 */ | |
548 | ||
549 | /* hardcode E1 also? */ | |
550 | /* -- according to dox, this is safer due to extra pulldowns? */ | |
551 | if (dev<2) { | |
552 | GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400, | |
553 | temp); /* 2408 */ | |
554 | } | |
555 | ||
556 | /* wake up MAC */ /* 2400 */ | |
557 | GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp); | |
558 | temp |= (1<<7); /* enable port */ | |
559 | #ifdef CONFIG_GT_USE_MAC_HASH_TABLE | |
560 | temp |= (1<<12); /* hash size 1/2k */ | |
561 | #else | |
562 | temp |= 1; /* promisc */ | |
563 | #endif | |
564 | GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp); | |
565 | /* 2400 */ | |
566 | ||
567 | #ifdef RESTART_AUTONEG | |
568 | check_phy_state(p); | |
569 | #endif | |
570 | ||
571 | printf("%s: Waiting for link up..\n", wp->name); | |
572 | temp = 10 * 1000; | |
573 | /* wait for link back up */ | |
574 | while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8) | |
575 | && (--temp > 0)){ | |
576 | udelay(1000); /* wait 1 ms */ | |
577 | } | |
578 | if ( temp == 0) { | |
579 | printf("%s: Failed!\n", wp->name); | |
580 | return (0); | |
581 | } | |
582 | ||
583 | printf("%s: OK!\n", wp->name); | |
584 | ||
585 | p->tdn = 0; | |
586 | p->rdn = 0; | |
587 | p->eth_tx_desc[p->tdn].command_status = 0; | |
588 | ||
589 | /* Initialize Rx Side */ | |
590 | for (temp = 0; temp < NR; temp++) { | |
77ddac94 | 591 | p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp]; |
5772de44 WD |
592 | p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16; |
593 | ||
594 | /* GT96100 Owner */ | |
595 | p->eth_rx_desc[temp].command_status = 0x80000000; | |
596 | p->eth_rx_desc[temp].next_desc = | |
597 | (struct eth0_rx_desc_struct *) | |
598 | &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count; | |
599 | } | |
600 | ||
601 | FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0], | |
602 | (unsigned int)&p->eth_tx_desc[NR]); | |
603 | FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0], | |
604 | (unsigned int)&p->eth_rx_desc[NR]); | |
605 | ||
606 | GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base, | |
607 | (unsigned int) p->eth_tx_desc); | |
608 | GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base, | |
609 | (unsigned int) p->eth_rx_desc); | |
610 | GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base, | |
611 | (unsigned int) p->eth_rx_desc); | |
612 | ||
613 | #ifdef DEBUG | |
614 | printf ("\nRx descriptor pointer is %08x %08x\n", | |
615 | GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base), | |
616 | GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base)); | |
617 | printf ("\n\n%08x %08x\n", | |
618 | (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status); | |
619 | ||
620 | printf ("Descriptor dump:\n"); | |
621 | printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status); | |
622 | printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count); | |
623 | printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer); | |
624 | printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc); | |
625 | printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0)); | |
626 | printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4)); | |
627 | printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8)); | |
628 | printf ("%08x\n\n", | |
629 | *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc)); | |
630 | #endif | |
631 | ||
632 | #ifdef DEBUG | |
633 | gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]); | |
634 | #endif | |
635 | ||
636 | #ifdef CONFIG_GT_USE_MAC_HASH_TABLE | |
637 | { | |
638 | unsigned int hashtable_base; | |
639 | u8 *b = (u8 *)(wp->enetaddr); | |
640 | u32 macH, macL; | |
641 | ||
642 | /* twist the MAC up into the way the discovery wants it */ | |
643 | macH= (b[0]<<8) | b[1]; | |
644 | macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5]; | |
645 | ||
646 | /* mode 0, size 0x800 */ | |
647 | hashtable_base =initAddressTable(dev,0,1); | |
648 | ||
649 | if(!hashtable_base) { | |
650 | printf("initAddressTable failed\n"); | |
651 | return 0; | |
652 | } | |
653 | ||
654 | addAddressTableEntry(dev, macH, macL, 1, 0); | |
655 | GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base, | |
656 | hashtable_base); | |
657 | } | |
658 | #endif | |
659 | ||
660 | /* Start Rx*/ | |
661 | GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080); | |
662 | printf("%s: gt6426x eth device %d init success \n", wp->name, dev ); | |
663 | return 1; | |
664 | } | |
665 | ||
666 | /* enter all the galileo ethernet devs into MULTI-BOOT */ | |
667 | void | |
668 | gt6426x_eth_initialize(bd_t *bis) | |
669 | { | |
670 | struct eth_device *dev; | |
671 | struct eth_dev_s *p; | |
672 | int devnum, x, temp; | |
673 | char *s, *e, buf[64]; | |
674 | ||
675 | #ifdef DEBUG | |
676 | printf( "\n%s\n", __FUNCTION ); | |
677 | #endif | |
678 | ||
679 | for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) { | |
680 | dev = calloc(sizeof(*dev), 1); | |
681 | if (!dev) { | |
682 | printf( "%s: gal_enet%d allocation failure, %s\n", | |
683 | __FUNCTION__, devnum, "eth_device structure"); | |
684 | return; | |
685 | } | |
686 | ||
687 | /* must be less than NAMESIZE (16) */ | |
688 | sprintf(dev->name, "gal_enet%d", devnum); | |
689 | ||
690 | #ifdef DEBUG | |
691 | printf( "Initializing %s\n", dev->name ); | |
692 | #endif | |
693 | ||
694 | /* Extract the MAC address from the environment */ | |
695 | switch (devnum) | |
696 | { | |
697 | case 0: s = "ethaddr"; break; | |
698 | #if (GAL_ETH_DEVS > 1) | |
699 | case 1: s = "eth1addr"; break; | |
700 | #endif | |
701 | #if (GAL_ETH_DEVS > 2) | |
702 | case 2: s = "eth2addr"; break; | |
703 | #endif | |
704 | default: /* this should never happen */ | |
705 | printf( "%s: Invalid device number %d\n", | |
706 | __FUNCTION__, devnum ); | |
707 | return; | |
708 | } | |
709 | ||
710 | temp = getenv_r (s, buf, sizeof(buf)); | |
711 | s = (temp > 0) ? buf : NULL; | |
712 | ||
713 | #ifdef DEBUG | |
714 | printf ("Setting MAC %d to %s\n", devnum, s ); | |
715 | #endif | |
716 | for (x = 0; x < 6; ++x) { | |
717 | dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0; | |
718 | if (s) | |
719 | s = (*e) ? e+1 : e; | |
720 | } | |
721 | ||
722 | dev->init = (void*)gt6426x_eth_probe; | |
723 | dev->halt = (void*)gt6426x_eth_reset; | |
724 | dev->send = (void*)gt6426x_eth_transmit; | |
725 | dev->recv = (void*)gt6426x_eth_poll; | |
726 | ||
77ddac94 WD |
727 | p = calloc( sizeof(*p), 1 ); |
728 | dev->priv = (void*)p; | |
5772de44 WD |
729 | if (!p) |
730 | { | |
731 | printf( "%s: %s allocation failure, %s\n", | |
732 | __FUNCTION__, dev->name, "Private Device Structure"); | |
733 | free(dev); | |
734 | return; | |
735 | } | |
736 | ||
737 | p->dev = devnum; | |
738 | p->tdn=0; | |
739 | p->rdn=0; | |
740 | p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS; | |
741 | ||
742 | p->eth_tx_desc = | |
743 | (eth0_tx_desc_single *) | |
744 | (((unsigned int) malloc(sizeof (eth0_tx_desc_single) * | |
745 | (NT+1)) & 0xfffffff0) + 0x10); | |
746 | if (!p) | |
747 | { | |
748 | printf( "%s: %s allocation failure, %s\n", | |
749 | __FUNCTION__, dev->name, "Tx Descriptor"); | |
750 | free(dev); | |
751 | return; | |
752 | } | |
753 | ||
754 | p->eth_rx_desc = | |
755 | (eth0_rx_desc_single *) | |
756 | (((unsigned int) malloc(sizeof (eth0_rx_desc_single) * | |
757 | (NR+1)) & 0xfffffff0) + 0x10); | |
758 | if (!p->eth_rx_desc) | |
759 | { | |
760 | printf( "%s: %s allocation failure, %s\n", | |
761 | __FUNCTION__, dev->name, "Rx Descriptor"); | |
762 | free(dev); | |
763 | free(p); | |
764 | return; | |
765 | } | |
766 | ||
767 | p->eth_tx_buffer = | |
768 | (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); | |
769 | if (!p->eth_tx_buffer) | |
770 | { | |
771 | printf( "%s: %s allocation failure, %s\n", | |
772 | __FUNCTION__, dev->name, "Tx Bufffer"); | |
773 | free(dev); | |
774 | free(p); | |
775 | free(p->eth_rx_desc); | |
776 | return; | |
777 | } | |
778 | ||
779 | for (temp = 0 ; temp < NR ; temp ++) { | |
780 | p->eth_rx_buffer[temp] = | |
781 | (char *) | |
782 | (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); | |
783 | if (!p->eth_rx_buffer[temp]) | |
784 | { | |
785 | printf( "%s: %s allocation failure, %s\n", | |
786 | __FUNCTION__, dev->name, "Rx Buffers"); | |
787 | free(dev); | |
788 | free(p); | |
789 | free(p->eth_tx_buffer); | |
790 | free(p->eth_rx_desc); | |
791 | free(p->eth_tx_desc); | |
792 | while (temp >= 0) | |
793 | free(p->eth_rx_buffer[--temp]); | |
794 | return; | |
795 | } | |
796 | } | |
797 | ||
798 | ||
799 | eth_register(dev); | |
b9307262 | 800 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c MB |
801 | miiphy_register(dev->name, |
802 | gt6426x_miiphy_read, gt6426x_miiphy_write); | |
803 | #endif | |
5772de44 | 804 | } |
63ff004c | 805 | |
5772de44 | 806 | } |
77a31854 | 807 | #endif |