[people/ms/u-boot.git] / board / fads / fads.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
 * and Dan Malek
 *
 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
 *
 * This header file contains values common to all FADS family boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/****************************************************************************
 * Flash Memory Map as used by U-Boot:
 *
 *                          Start Address    Length
 * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
 * |                       | 0xFE00_0100     Reset Vector
 * +                       + 0xFE0?_????
 * | U-Boot code           |
 * |                       |
 * +-----------------------+ 0xFE04_0000 (sector border)
 * |                       |
 * |                       |
 * | U-Boot environment    |
 * |                       |                                 ^
 * |                       |                                 | U-Boot
 * +=======================+ 0xFE08_0000 (sector border)    -----------------
 * | Available             |                                 | Applications
 * | ...                   |                                 v
 *
 *****************************************************************************/

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_ENV_OVERWRITE

#define CONFIG_NFSBOOTCOMMAND							\
    "dhcp;"									\
    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "			\
    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
    "bootm"

#define CONFIG_BOOTCOMMAND							\
    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
    "bootm fe080000"

#undef CONFIG_BOOTARGS

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#if !defined(CONFIG_MPC885ADS)
#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
#endif

/*
 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
 * got FEC so FEC is the default.
 */
#ifndef CONFIG_ADS
#undef	CONFIG_SCC1_ENET		/* Disable SCC1 ethernet */
#define	CONFIG_FEC_ENET			/* Use FEC ethernet  */
#else					/* Old ADS has not got FEC option */
#define	CONFIG_SCC1_ENET		/* Use SCC1 ethernet */
#undef	CONFIG_FEC_ENET			/* No FEC ethernet  */
#endif /* !CONFIG_ADS */

#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif

#ifdef CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_PING

#endif


/*
 * Miscellaneous configurable options
 */
#define	CFG_PROMPT		"=>"		/* Monitor Command Prompt	*/
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define	CFG_LONGHELP				/* #undef to save memory	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size	*/
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_LOAD_ADDR	 	0x00100000

#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
#define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
/*
 * 2048	SDRAM rows
 * 1000	factor s -> ms
 * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4	Number of refresh cycles per period
 * 64	Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
#elif defined(CONFIG_FADS)				/* Old/new FADS */
#define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
#else							/* Old ADS */
#define	CFG_SDRAM_SIZE		0x00000000		/* No SDRAM */
#endif

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#if (CFG_SDRAM_SIZE)
#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
#else
#define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
#endif /* CFG_SDRAM_SIZE */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

#define CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/

#ifdef CONFIG_BZIP2
#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
#else
#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
#endif /* CONFIG_BZIP2 */

/*-----------------------------------------------------------------------
 * Flash organization
 */
#define CFG_FLASH_BASE		CFG_MONITOR_BASE
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/

#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
#define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/
#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */

#define	CFG_DIRECT_FLASH_TFTP

#if defined(CONFIG_CMD_JFFS2)

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
#define MTDPARTS_DEFAULT	"mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
*/

#define CFG_JFFS2_SORT_FRAGMENTS
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/

/*-----------------------------------------------------------------------
 * I2C configuration
 */
#if defined(CONFIG_CMD_I2C)
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE		0x7F
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	SCCR_TBS

/*-----------------------------------------------------------------------
 * DER - Debug Enable Register
 *-----------------------------------------------------------------------
 * Set to zero to prevent the processor from entering debug mode
 */
#define CFG_DER		 0

/* Because of the way the 860 starts up and assigns CS0 the entire
 * address space, we have to set the memory controller differently.
 * Normally, you write the option register first, and then enable the
 * chip select by writing the base register.  For CS0, you must write
 * the base register first, followed by the option register.
 */

/*
 * Init Memory Controller:
 *
 * BR0/OR0 (Flash)
 * BR1/OR1 (BCSR)
 */
/* the other CS:s are determined by looking at parameters in BCSRx */

#define BCSR_ADDR		((uint) 0xFF080000)

#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )

/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_PRELIM	0xFFFF8110		/* 64Kbyte address space */
#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/* values according to the manual */

#define	BCSR0			((uint) (BCSR_ADDR + 0x00))
#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
#define	BCSR4			((uint) (BCSR_ADDR + 0x10))

/*
 * (F)ADS bitvalues by Helmut Buchsbaum
 *
 * See User's Manual for a proper
 * description of the following structures
 */

#define BCSR0_ERB       ((uint)0x80000000)
#define BCSR0_IP        ((uint)0x40000000)
#define BCSR0_BDIS      ((uint)0x10000000)
#define BCSR0_BPS_MASK  ((uint)0x0C000000)
#define BCSR0_ISB_MASK  ((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)

#define BCSR1_FLASH_EN           ((uint)0x80000000)
#define BCSR1_DRAM_EN            ((uint)0x40000000)
#define BCSR1_ETHEN              ((uint)0x20000000)
#define BCSR1_IRDEN              ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN            ((uint)0x02000000)
#define BCSR1_RS232EN_1          ((uint)0x01000000)
#define BCSR1_PCCEN              ((uint)0x00800000)
#define BCSR1_PCCVCC0            ((uint)0x00400000)
#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
#define BCSR1_RS232EN_2          ((uint)0x00040000)
#define BCSR1_SDRAM_EN           ((uint)0x00020000)
#define BCSR1_PCCVCC1            ((uint)0x00010000)

#define BCSR1_PCCVCCON		 BCSR1_PCCVCC0

#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
#define BCSR2_FLASH_PD_SHIFT     28
#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT      23
#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)

#define BCSR3_DBID_MASK          ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0            ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
#define BCSR3_BREVN1             ((ushort)0x0008)
#define BCSR3_BREVN2_MASK        ((ushort)0x0003)

#define BCSR4_ETHLOOP            ((uint)0x80000000)
#define BCSR4_TFPLDL             ((uint)0x40000000)
#define BCSR4_TPSQEL             ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
#if defined(CONFIG_MPC823)
#define BCSR4_USB_EN             ((uint)0x08000000)
#define BCSR4_USB_SPEED          ((uint)0x04000000)
#define BCSR4_VCCO               ((uint)0x02000000)
#define BCSR4_VIDEO_ON           ((uint)0x00800000)
#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
#define BCSR4_VIDEO_RST          ((uint)0x00200000)
#define BCSR4_MODEM_EN           ((uint)0x00100000)
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#elif defined(CONFIG_MPC850)
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#elif defined(CONFIG_MPC860SAR)
#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
#else /* MPC860T and other chips with FEC */
#define BCSR4_FETH_EN            ((uint)0x08000000)
#define BCSR4_FETHCFG0           ((uint)0x04000000)
#define BCSR4_FETHFDE            ((uint)0x02000000)
#define BCSR4_FETHCFG1           ((uint)0x00400000)
#define BCSR4_FETHRST            ((uint)0x00200000)
#endif

/* BSCR5 exists on MPC86xADS and MPC885ADS only */

#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)

#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)

#define BCSR5_MII2_EN		0x40
#define BCSR5_MII2_RST		0x20
#define BCSR5_T1_RST		0x10
#define BCSR5_ATM155_RST	0x08
#define BCSR5_ATM25_RST		0x04
#define BCSR5_MII1_EN		0x02
#define BCSR5_MII1_RST		0x01

/* We don't use the 8259.
*/
#define NR_8259_INTS	0

/* Machine type
*/
#define _MACH_8xx (_MACH_fads)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_MAC_PARTITION    1
#define CONFIG_DOS_PARTITION    1
#define CONFIG_ISO_PARTITION	1

#undef	CONFIG_ATAPI
#if 0	/* does not make sense when CONFIG_CMD_IDE is not enabled, too */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
#endif
#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
#define CFG_ATA_IDE0_OFFSET	0x0000

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0000

#define CONFIG_DISK_SPINUP_TIME 1000000
/* #undef CONFIG_DISK_SPINUP_TIME */	/* usin  Compact Flash */
Commit	Line	Data
2d39b71f	1	/*
180d3f74	2	* (C) Copyright 2000-2004
2d39b71f WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
2d39b71f WD	4	*
180d3f74 WD	5	* Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
	6	* and Dan Malek
	7	*
	8	* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
	9	*
	10	* This header file contains values common to all FADS family boards.
	11	*
2d39b71f WD	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	/****************************************************************************
180d3f74	32	* Flash Memory Map as used by U-Boot:
2d39b71f WD	33	*
	34	* Start Address Length
	35	* +-----------------------+ 0xFE00_0000 Start of Flash -----------------
180d3f74 WD	36	* \| \| 0xFE00_0100 Reset Vector
	37	* + + 0xFE0?_????
	38	* \| U-Boot code \|
	39	* \| \|
	40	* +-----------------------+ 0xFE04_0000 (sector border)
	41	* \| \|
	42	* \| \|
	43	* \| U-Boot environment \|
	44	* \| \| ^
	45	* \| \| \| U-Boot
	46	* +=======================+ 0xFE08_0000 (sector border) -----------------
	47	* \| Available \| \| Applications
2d39b71f WD	48	* \| ... \| v
	49	*
	50	*****************************************************************************/
180d3f74 WD	51
	52	#if 0
	53	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	54	#else
	55	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	56	#endif
	57
8ff0208d WD	58	#define CONFIG_ENV_OVERWRITE
	59
	60	#define CONFIG_NFSBOOTCOMMAND \
180d3f74	61	"dhcp;" \
8ff0208d WD	62	"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
8ff0208d WD	63	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
180d3f74 WD	64	"bootm"
180d3f74 WD	65
8ff0208d WD	66	#define CONFIG_BOOTCOMMAND \
	67	"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
	68	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
	69	"bootm fe080000"
	70
	71	#undef CONFIG_BOOTARGS
	72
180d3f74	73	#undef CONFIG_WATCHDOG /* watchdog disabled */
78f9fef7 SW	74
78f9fef7 SW	75	#if !defined(CONFIG_MPC885ADS)
1114257c	76	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
78f9fef7	77	#endif
180d3f74 WD	78
180d3f74 WD	79	/*
8ff0208d	80	* New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
180d3f74 WD	81	* 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
	82	* motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
	83	* got FEC so FEC is the default.
	84	*/
	85	#ifndef CONFIG_ADS
	86	#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
	87	#define CONFIG_FEC_ENET /* Use FEC ethernet */
	88	#else /* Old ADS has not got FEC option */
	89	#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
	90	#undef CONFIG_FEC_ENET /* No FEC ethernet */
	91	#endif /* !CONFIG_ADS */
	92
	93	#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
	94	#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
	95	#endif
	96
	97	#ifdef CONFIG_FEC_ENET
	98	#define CFG_DISCOVER_PHY
	99	#endif
	100
079a136c JL	101
	102	/*
	103	* BOOTP options
	104	*/
	105	#define CONFIG_BOOTP_BOOTFILESIZE
	106	#define CONFIG_BOOTP_BOOTPATH
	107	#define CONFIG_BOOTP_GATEWAY
	108	#define CONFIG_BOOTP_HOSTNAME
	109
	110
498ff9a2 JL	111	#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
	112	/*
	113	* Command line configuration.
	114	*/
	115	#include <config_cmd_default.h>
	116
	117	#define CONFIG_CMD_ASKENV
	118	#define CONFIG_CMD_DHCP
	119	#define CONFIG_CMD_ECHO
	120	#define CONFIG_CMD_IMMAP
	121	#define CONFIG_CMD_JFFS2
	122	#define CONFIG_CMD_MII
	123	#define CONFIG_CMD_PCMCIA
	124	#define CONFIG_CMD_PING
	125
	126	#endif
180d3f74	127
180d3f74 WD	128
	129	/*
	130	* Miscellaneous configurable options
	131	*/
8ff0208d WD	132	#define CFG_PROMPT "=>" /* Monitor Command Prompt */
	133	#define CFG_HUSH_PARSER
	134	#define CFG_PROMPT_HUSH_PS2 "> "
	135	#define CFG_LONGHELP /* #undef to save memory */
c508a4ce	136	#if defined(CONFIG_CMD_KGDB)
8ff0208d	137	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
180d3f74	138	#else
8ff0208d	139	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
180d3f74	140	#endif
8ff0208d WD	141	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
	142	#define CFG_MAXARGS 16 /* max number of command args */
	143	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
180d3f74 WD	144
	145	#define CFG_LOAD_ADDR 0x00100000
	146
	147	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	148
	149	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	150
	151	/*
	152	* Low Level Configuration Settings
	153	* (address mappings, register initial values, etc.)
	154	* You should know what you are doing if you make changes here.
	155	*/
8ff0208d	156
180d3f74 WD	157	/*-----------------------------------------------------------------------
	158	* Internal Memory Mapped Register
	159	*/
	160	#define CFG_IMMR 0xFF000000
	161
	162	/*-----------------------------------------------------------------------
	163	* Definitions for initial stack pointer and data area (in DPRAM)
	164	*/
	165	#define CFG_INIT_RAM_ADDR CFG_IMMR
	166	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	167	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	168	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	169	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	170
	171	/*-----------------------------------------------------------------------
	172	* Start addresses for the final memory configuration
	173	* (Set up by the startup code)
	174	* Please note that CFG_SDRAM_BASE _must_ start at 0
	175	*/
	176	#define CFG_SDRAM_BASE 0x00000000
1114257c	177	#if defined(CONFIG_MPC86xADS) \|\| defined(CONFIG_MPC885ADS) /* New ADS or Duet */
180d3f74	178	#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
8ff0208d WD	179	/*
	180	* 2048 SDRAM rows
	181	* 1000 factor s -> ms
	182	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
	183	* 4 Number of refresh cycles per period
	184	* 64 Refresh cycle in ms per number of rows
	185	*/
	186	#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
180d3f74 WD	187	#elif defined(CONFIG_FADS) /* Old/new FADS */
	188	#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
	189	#else /* Old ADS */
	190	#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
	191	#endif
	192
	193	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	194	#if (CFG_SDRAM_SIZE)
	195	#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
	196	#else
	197	#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
	198	#endif /* CFG_SDRAM_SIZE */
	199
	200	/*
	201	* For booting Linux, the board info and command line data
	202	* have to be in the first 8 MB of memory, since this is
	203	* the maximum mapped by the Linux kernel during initialization.
	204	*/
	205	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
99edcfb2 WD	206
	207	#define CFG_MONITOR_BASE TEXT_BASE
	208	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
	209
	210	#ifdef CONFIG_BZIP2
	211	#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
	212	#else
	213	#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
	214	#endif /* CONFIG_BZIP2 */
	215
180d3f74 WD	216	/*-----------------------------------------------------------------------
	217	* Flash organization
	218	*/
99edcfb2 WD	219	#define CFG_FLASH_BASE CFG_MONITOR_BASE
99edcfb2 WD	220	#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
180d3f74	221
99edcfb2 WD	222	#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
99edcfb2 WD	223	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
180d3f74 WD	224
	225	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	226	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	227
	228	#define CFG_ENV_IS_IN_FLASH 1
	229	#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
	230	#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
	231	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
67c31036	232	#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
180d3f74	233
99edcfb2	234	#define CFG_DIRECT_FLASH_TFTP
1114257c	235
c508a4ce	236	#if defined(CONFIG_CMD_JFFS2)
700a0c64 WD	237
	238	/*
	239	* JFFS2 partitions
	240	*
	241	*/
	242	/* No command line, one static partition, whole device */
	243	#undef CONFIG_JFFS2_CMDLINE
	244	#define CONFIG_JFFS2_DEV "nor0"
	245	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	246	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	247
	248	/* mtdparts command line support */
	249	/* Note: fake mtd_id used, no linux mtd map file */
	250	/*
	251	#define CONFIG_JFFS2_CMDLINE
	252	#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
	253	#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
	254	*/
	255
99edcfb2	256	#define CFG_JFFS2_SORT_FRAGMENTS
77a31854	257	#endif
180d3f74 WD	258
	259	/*-----------------------------------------------------------------------
	260	* Cache Configuration
	261	*/
	262	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
180d3f74	263	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
180d3f74 WD	264
	265	/*-----------------------------------------------------------------------
	266	* I2C configuration
	267	*/
c508a4ce	268	#if defined(CONFIG_CMD_I2C)
180d3f74 WD	269	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	270	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
	271	#define CFG_I2C_SLAVE 0x7F
	272	#endif
	273
	274	/*-----------------------------------------------------------------------
	275	* SYPCR - System Protection Control 11-9
	276	* SYPCR can only be written once after reset!
	277	*-----------------------------------------------------------------------
	278	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	279	*/
	280	#if defined(CONFIG_WATCHDOG)
	281	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	282	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	283	#else
	284	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	285	#endif
	286
	287	/*-----------------------------------------------------------------------
	288	* SIUMCR - SIU Module Configuration 11-6
	289	*-----------------------------------------------------------------------
	290	* PCMCIA config., multi-function pin tri-state
	291	*/
	292	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	293
	294	/*-----------------------------------------------------------------------
	295	* TBSCR - Time Base Status and Control 11-26
	296	*-----------------------------------------------------------------------
	297	* Clear Reference Interrupt Status, Timebase freezing enabled
	298	*/
	299	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
	300
	301	/*-----------------------------------------------------------------------
	302	* PISCR - Periodic Interrupt Status and Control 11-31
	303	*-----------------------------------------------------------------------
	304	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	305	*/
	306	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	307
	308	/*-----------------------------------------------------------------------
	309	* SCCR - System Clock and reset Control Register 15-27
	310	*-----------------------------------------------------------------------
	311	* Set clock output, timebase and RTC source and divider,
	312	* power management and some other internal clocks
	313	*/
	314	#define SCCR_MASK SCCR_EBDF11
8ff0208d	315	#define CFG_SCCR SCCR_TBS
180d3f74	316
1114257c	317	/*-----------------------------------------------------------------------
8ff0208d	318	* DER - Debug Enable Register
1114257c	319	*-----------------------------------------------------------------------
8ff0208d	320	* Set to zero to prevent the processor from entering debug mode
180d3f74 WD	321	*/
	322	#define CFG_DER 0
	323
8ff0208d WD	324	/* Because of the way the 860 starts up and assigns CS0 the entire
	325	* address space, we have to set the memory controller differently.
	326	* Normally, you write the option register first, and then enable the
	327	* chip select by writing the base register. For CS0, you must write
	328	* the base register first, followed by the option register.
	329	*/
180d3f74 WD	330
	331	/*
	332	* Init Memory Controller:
	333	*
	334	* BR0/OR0 (Flash)
	335	* BR1/OR1 (BCSR)
	336	*/
	337	/* the other CS:s are determined by looking at parameters in BCSRx */
	338
	339	#define BCSR_ADDR ((uint) 0xFF080000)
	340
	341	#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
	342
	343	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
	344	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
	345
	346	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
	347	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) \| BR_V )
	348
	349	/* BCSRx - Board Control and Status Registers */
	350	#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
	351	#define CFG_BR1_PRELIM ((BCSR_ADDR) \| BR_V)
	352
	353	/*
	354	* Internal Definitions
	355	*
	356	* Boot Flags
	357	*/
	358	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	359	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	360
	361	/* values according to the manual */
	362
180d3f74 WD	363	#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
	364	#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
	365	#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
	366	#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
	367	#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
	368
	369	/*
	370	* (F)ADS bitvalues by Helmut Buchsbaum
	371	*
	372	* See User's Manual for a proper
	373	* description of the following structures
	374	*/
	375
	376	#define BCSR0_ERB ((uint)0x80000000)
	377	#define BCSR0_IP ((uint)0x40000000)
	378	#define BCSR0_BDIS ((uint)0x10000000)
	379	#define BCSR0_BPS_MASK ((uint)0x0C000000)
	380	#define BCSR0_ISB_MASK ((uint)0x01800000)
	381	#define BCSR0_DBGC_MASK ((uint)0x00600000)
	382	#define BCSR0_DBPC_MASK ((uint)0x00180000)
	383	#define BCSR0_EBDF_MASK ((uint)0x00060000)
	384
	385	#define BCSR1_FLASH_EN ((uint)0x80000000)
	386	#define BCSR1_DRAM_EN ((uint)0x40000000)
	387	#define BCSR1_ETHEN ((uint)0x20000000)
	388	#define BCSR1_IRDEN ((uint)0x10000000)
	389	#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
	390	#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
	391	#define BCSR1_BCSR_EN ((uint)0x02000000)
	392	#define BCSR1_RS232EN_1 ((uint)0x01000000)
	393	#define BCSR1_PCCEN ((uint)0x00800000)
	394	#define BCSR1_PCCVCC0 ((uint)0x00400000)
	395	#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
	396	#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
	397	#define BCSR1_RS232EN_2 ((uint)0x00040000)
	398	#define BCSR1_SDRAM_EN ((uint)0x00020000)
	399	#define BCSR1_PCCVCC1 ((uint)0x00010000)
	400
	401	#define BCSR1_PCCVCCON BCSR1_PCCVCC0
	402
	403	#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
99edcfb2	404	#define BCSR2_FLASH_PD_SHIFT 28
180d3f74 WD	405	#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
	406	#define BCSR2_DRAM_PD_SHIFT 23
	407	#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
	408	#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
	409
	410	#define BCSR3_DBID_MASK ((ushort)0x3800)
	411	#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
	412	#define BCSR3_BREVNR0 ((ushort)0x0080)
	413	#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
	414	#define BCSR3_BREVN1 ((ushort)0x0008)
	415	#define BCSR3_BREVN2_MASK ((ushort)0x0003)
	416
	417	#define BCSR4_ETHLOOP ((uint)0x80000000)
	418	#define BCSR4_TFPLDL ((uint)0x40000000)
	419	#define BCSR4_TPSQEL ((uint)0x20000000)
	420	#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
8ff0208d	421	#if defined(CONFIG_MPC823)
180d3f74	422	#define BCSR4_USB_EN ((uint)0x08000000)
180d3f74	423	#define BCSR4_USB_SPEED ((uint)0x04000000)
180d3f74	424	#define BCSR4_VCCO ((uint)0x02000000)
180d3f74	425	#define BCSR4_VIDEO_ON ((uint)0x00800000)
180d3f74	426	#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
180d3f74	427	#define BCSR4_VIDEO_RST ((uint)0x00200000)
180d3f74	428	#define BCSR4_MODEM_EN ((uint)0x00100000)
180d3f74	429	#define BCSR4_DATA_VOICE ((uint)0x00080000)
8ff0208d	430	#elif defined(CONFIG_MPC850)
180d3f74	431	#define BCSR4_DATA_VOICE ((uint)0x00080000)
8ff0208d WD	432	#elif defined(CONFIG_MPC860SAR)
	433	#define BCSR4_UTOPIA_EN ((uint)0x08000000)
	434	#else /* MPC860T and other chips with FEC */
	435	#define BCSR4_FETH_EN ((uint)0x08000000)
	436	#define BCSR4_FETHCFG0 ((uint)0x04000000)
	437	#define BCSR4_FETHFDE ((uint)0x02000000)
	438	#define BCSR4_FETHCFG1 ((uint)0x00400000)
	439	#define BCSR4_FETHRST ((uint)0x00200000)
	440	#endif
180d3f74	441
8ff0208d	442	/* BSCR5 exists on MPC86xADS and MPC885ADS only */
1114257c WD	443
	444	#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
	445
	446	#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
	447
	448	#define BCSR5_MII2_EN 0x40
	449	#define BCSR5_MII2_RST 0x20
	450	#define BCSR5_T1_RST 0x10
	451	#define BCSR5_ATM155_RST 0x08
	452	#define BCSR5_ATM25_RST 0x04
	453	#define BCSR5_MII1_EN 0x02
	454	#define BCSR5_MII1_RST 0x01
	455
180d3f74 WD	456	/* We don't use the 8259.
	457	*/
	458	#define NR_8259_INTS 0
	459
	460	/* Machine type
	461	*/
	462	#define _MACH_8xx (_MACH_fads)
	463
	464	/*-----------------------------------------------------------------------
	465	* PCMCIA stuff
	466	*-----------------------------------------------------------------------
	467	*/
180d3f74 WD	468	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
	469	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
	470	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
	471	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
	472	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
	473	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	474	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
	475	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
	476
	477	/*-----------------------------------------------------------------------
	478	* IDE/ATA stuff
	479	*-----------------------------------------------------------------------
	480	*/
	481	#define CONFIG_MAC_PARTITION 1
	482	#define CONFIG_DOS_PARTITION 1
	483	#define CONFIG_ISO_PARTITION 1
	484
	485	#undef CONFIG_ATAPI
77a31854	486	#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
180d3f74	487	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
966083e9	488	#endif
180d3f74 WD	489	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	490	#undef CONFIG_IDE_LED /* LED for ide not supported */
	491	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	492
	493	#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
	494	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS2) / max. 2 drives per IDE bus */
	495
	496	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	497	#define CFG_ATA_IDE0_OFFSET 0x0000
	498
	499	/* Offset for data I/O */
	500	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
	501	/* Offset for normal register accesses */
	502	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
	503	/* Offset for alternate registers */
	504	#define CFG_ATA_ALT_OFFSET 0x0000
	505
	506	#define CONFIG_DISK_SPINUP_TIME 1000000
8ff0208d	507	/* #undef CONFIG_DISK_SPINUP_TIME / / usin Compact Flash */