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41d91011 PK |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
41d91011 PK |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/mmu.h> | |
9 | #include <asm/immap_85xx.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/fsl_ddr_sdram.h> | |
12 | #include <asm/fsl_ddr_dimm_params.h> | |
13 | #include <asm/io.h> | |
14 | #include <asm/fsl_law.h> | |
15 | ||
16 | DECLARE_GLOBAL_DATA_PTR; | |
17 | ||
18 | #ifndef CONFIG_SYS_DDR_RAW_TIMING | |
19 | ||
20 | fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { | |
21 | .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, | |
22 | .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, | |
23 | .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, | |
24 | .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, | |
25 | .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, | |
26 | .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, | |
27 | .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, | |
28 | .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, | |
29 | .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, | |
30 | .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, | |
31 | .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, | |
32 | .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, | |
33 | .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, | |
34 | .ddr_data_init = CONFIG_MEM_INIT_VALUE, | |
35 | .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, | |
36 | .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, | |
37 | .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, | |
38 | .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, | |
39 | .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, | |
40 | .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, | |
41 | .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, | |
42 | .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, | |
43 | .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, | |
44 | .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 | |
45 | }; | |
46 | ||
47 | fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = { | |
48 | .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, | |
49 | .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, | |
50 | .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, | |
51 | .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333, | |
52 | .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333, | |
53 | .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333, | |
54 | .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333, | |
55 | .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, | |
56 | .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, | |
57 | .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333, | |
58 | .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333, | |
59 | .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, | |
60 | .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333, | |
61 | .ddr_data_init = CONFIG_MEM_INIT_VALUE, | |
62 | .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333, | |
63 | .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, | |
64 | .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, | |
65 | .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, | |
66 | .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, | |
67 | .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, | |
68 | .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333, | |
69 | .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, | |
70 | .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, | |
71 | .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 | |
72 | }; | |
73 | ||
74 | ||
75 | fixed_ddr_parm_t fixed_ddr_parm_0[] = { | |
76 | {750, 850, &ddr_cfg_regs_800}, | |
77 | {1060, 1333, &ddr_cfg_regs_1333}, | |
78 | {0, 0, NULL} | |
79 | }; | |
80 | ||
81 | /* | |
82 | * Fixed sdram init -- doesn't use serial presence detect. | |
83 | */ | |
84 | phys_size_t fixed_sdram(void) | |
85 | { | |
86 | int i; | |
87 | char buf[32]; | |
88 | fsl_ddr_cfg_regs_t ddr_cfg_regs; | |
89 | phys_size_t ddr_size; | |
90 | ulong ddr_freq, ddr_freq_mhz; | |
91 | ||
92 | ddr_freq = get_ddr_freq(0); | |
93 | ddr_freq_mhz = ddr_freq / 1000000; | |
94 | ||
95 | printf("Configuring DDR for %s MT/s data rate\n", | |
96 | strmhz(buf, ddr_freq)); | |
97 | ||
98 | for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { | |
99 | if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && | |
100 | (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { | |
101 | memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, | |
102 | sizeof(ddr_cfg_regs)); | |
103 | break; | |
104 | } | |
105 | } | |
106 | ||
107 | if (fixed_ddr_parm_0[i].max_freq == 0) | |
108 | panic("Unsupported DDR data rate %s MT/s data rate\n", | |
109 | strmhz(buf, ddr_freq)); | |
110 | ||
111 | ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; | |
112 | fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); | |
113 | ||
114 | if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, | |
115 | LAW_TRGT_IF_DDR_1) < 0) { | |
116 | printf("ERROR setting Local Access Windows for DDR\n"); | |
117 | return 0; | |
118 | } | |
119 | ||
120 | return ddr_size; | |
121 | } | |
122 | ||
123 | #else /* CONFIG_SYS_DDR_RAW_TIMING */ | |
124 | /* Micron MT41J512M8_187E */ | |
125 | dimm_params_t ddr_raw_timing = { | |
126 | .n_ranks = 1, | |
127 | .rank_density = 1073741824u, | |
128 | .capacity = 1073741824u, | |
129 | .primary_sdram_width = 32, | |
130 | .ec_sdram_width = 0, | |
131 | .registered_dimm = 0, | |
132 | .mirrored_dimm = 0, | |
133 | .n_row_addr = 15, | |
134 | .n_col_addr = 10, | |
135 | .n_banks_per_sdram_device = 8, | |
136 | .edc_config = 0, | |
137 | .burst_lengths_bitmask = 0x0c, | |
138 | ||
139 | .tCKmin_X_ps = 1870, | |
140 | .caslat_X = 0x1e << 4, /* 5,6,7,8 */ | |
141 | .tAA_ps = 13125, | |
142 | .tWR_ps = 15000, | |
143 | .tRCD_ps = 13125, | |
144 | .tRRD_ps = 7500, | |
145 | .tRP_ps = 13125, | |
146 | .tRAS_ps = 37500, | |
147 | .tRC_ps = 50625, | |
148 | .tRFC_ps = 160000, | |
149 | .tWTR_ps = 7500, | |
150 | .tRTP_ps = 7500, | |
151 | .refresh_rate_ps = 7800000, | |
152 | .tFAW_ps = 37500, | |
153 | }; | |
154 | ||
155 | int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, | |
156 | unsigned int controller_number, | |
157 | unsigned int dimm_number) | |
158 | { | |
159 | const char dimm_model[] = "Fixed DDR on board"; | |
160 | ||
161 | if ((controller_number == 0) && (dimm_number == 0)) { | |
162 | memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); | |
163 | memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); | |
164 | memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); | |
165 | } | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | void fsl_ddr_board_options(memctl_options_t *popts, | |
171 | dimm_params_t *pdimm, | |
172 | unsigned int ctrl_num) | |
173 | { | |
174 | int i; | |
175 | popts->clk_adjust = 6; | |
176 | popts->cpo_override = 0x1f; | |
177 | popts->write_data_delay = 2; | |
178 | popts->half_strength_driver_enable = 1; | |
179 | /* Write leveling override */ | |
180 | popts->wrlvl_en = 1; | |
181 | popts->wrlvl_override = 1; | |
182 | popts->wrlvl_sample = 0xf; | |
183 | popts->wrlvl_start = 0x8; | |
184 | popts->trwt_override = 1; | |
185 | popts->trwt = 0; | |
186 | ||
187 | for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { | |
188 | popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; | |
189 | popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; | |
190 | } | |
191 | } | |
192 | ||
193 | #endif /* CONFIG_SYS_DDR_RAW_TIMING */ |