[thirdparty/u-boot.git] / board / freescale / bsc9132qds / ddr.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>

#ifndef CONFIG_SYS_DDR_RAW_TIMING

fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};

fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};


fixed_ddr_parm_t fixed_ddr_parm_0[] = {
	{750, 850, &ddr_cfg_regs_800},
	{1060, 1333, &ddr_cfg_regs_1333},
	{0, 0, NULL}
};

/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
phys_size_t fixed_sdram(void)
{
	int i;
	char buf[32];
	fsl_ddr_cfg_regs_t ddr_cfg_regs;
	phys_size_t ddr_size;
	ulong ddr_freq, ddr_freq_mhz;

	ddr_freq = get_ddr_freq(0);
	ddr_freq_mhz = ddr_freq / 1000000;

	printf("Configuring DDR for %s MT/s data rate\n",
				strmhz(buf, ddr_freq));

	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
							sizeof(ddr_cfg_regs));
			break;
		}
	}

	if (fixed_ddr_parm_0[i].max_freq == 0)
		panic("Unsupported DDR data rate %s MT/s data rate\n",
					strmhz(buf, ddr_freq));

	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
					LAW_TRGT_IF_DDR_1) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	}

	return ddr_size;
}

#else /* CONFIG_SYS_DDR_RAW_TIMING */
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
	.n_ranks = 1,
	.rank_density = 1073741824u,
	.capacity = 1073741824u,
	.primary_sdram_width = 32,
	.ec_sdram_width = 0,
	.registered_dimm = 0,
	.mirrored_dimm = 0,
	.n_row_addr = 15,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 0,
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1870,
	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
	.taa_ps = 13125,
	.twr_ps = 15000,
	.trcd_ps = 13125,
	.trrd_ps = 7500,
	.trp_ps = 13125,
	.tras_ps = 37500,
	.trc_ps = 50625,
	.trfc_ps = 160000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 37500,
};

int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
		unsigned int controller_number,
		unsigned int dimm_number)
{
	const char dimm_model[] = "Fixed DDR on board";

	if ((controller_number == 0) && (dimm_number == 0)) {
		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
	}

	return 0;
}

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	int i;
	popts->clk_adjust = 6;
	popts->cpo_override = 0x1f;
	popts->write_data_delay = 2;
	popts->half_strength_driver_enable = 1;
	/* Write leveling override */
	popts->wrlvl_en = 1;
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;
	popts->wrlvl_start = 0x8;
	popts->trwt_override = 1;
	popts->trwt = 0;

	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
	}
}

#endif /* CONFIG_SYS_DDR_RAW_TIMING */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
41d91011 PK	2	/*
41d91011 PK	3	* Copyright 2013 Freescale Semiconductor, Inc.
41d91011 PK	4	*/
	5
	6	#include <common.h>
	7	#include <asm/mmu.h>
	8	#include <asm/immap_85xx.h>
	9	#include <asm/processor.h>
5614e71b YS	10	#include <fsl_ddr_sdram.h>
5614e71b YS	11	#include <fsl_ddr_dimm_params.h>
41d91011 PK	12	#include <asm/io.h>
	13	#include <asm/fsl_law.h>
	14
41d91011 PK	15	#ifndef CONFIG_SYS_DDR_RAW_TIMING
	16
	17	fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
	18	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
	19	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
	20	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
	21	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
	22	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
	23	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
	24	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
	25	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
	26	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
	27	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
	28	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
	29	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
	30	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
	31	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
	32	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
	33	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
	34	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
	35	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
	36	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
	37	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
	38	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
	39	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
	40	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
	41	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
	42	};
	43
	44	fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
	45	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
	46	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
	47	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
	48	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
	49	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
	50	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
	51	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
	52	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
	53	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
	54	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
	55	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
	56	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
	57	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
	58	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
	59	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
	60	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
	61	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
	62	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
	63	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
	64	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
	65	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
	66	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
	67	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
	68	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
	69	};
	70
	71
	72	fixed_ddr_parm_t fixed_ddr_parm_0[] = {
	73	{750, 850, &ddr_cfg_regs_800},
	74	{1060, 1333, &ddr_cfg_regs_1333},
	75	{0, 0, NULL}
	76	};
	77
	78	/*
79	* Fixed sdram init -- doesn't use serial presence detect.
80	*/
81	phys_size_t fixed_sdram(void)
82	{
83	int i;
84	char buf[32];
85	fsl_ddr_cfg_regs_t ddr_cfg_regs;
86	phys_size_t ddr_size;
87	ulong ddr_freq, ddr_freq_mhz;
88
89	ddr_freq = get_ddr_freq(0);
90	ddr_freq_mhz = ddr_freq / 1000000;
91
92	printf("Configuring DDR for %s MT/s data rate\n",
93	strmhz(buf, ddr_freq));
94
95	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
96	if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
97	(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
98	memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
99	sizeof(ddr_cfg_regs));
100	break;
101	}
102	}
103
104	if (fixed_ddr_parm_0[i].max_freq == 0)
105	panic("Unsupported DDR data rate %s MT/s data rate\n",
106	strmhz(buf, ddr_freq));
107
108	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
c63e1370	109	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
41d91011 PK	110
	111	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
	112	LAW_TRGT_IF_DDR_1) < 0) {
	113	printf("ERROR setting Local Access Windows for DDR\n");
	114	return 0;
	115	}
	116
	117	return ddr_size;
	118	}
	119
	120	#else /* CONFIG_SYS_DDR_RAW_TIMING */
	121	/* Micron MT41J512M8_187E */
	122	dimm_params_t ddr_raw_timing = {
	123	.n_ranks = 1,
	124	.rank_density = 1073741824u,
	125	.capacity = 1073741824u,
	126	.primary_sdram_width = 32,
	127	.ec_sdram_width = 0,
	128	.registered_dimm = 0,
	129	.mirrored_dimm = 0,
	130	.n_row_addr = 15,
	131	.n_col_addr = 10,
	132	.n_banks_per_sdram_device = 8,
	133	.edc_config = 0,
	134	.burst_lengths_bitmask = 0x0c,
	135
0dd38a35 PJ	136	.tckmin_x_ps = 1870,
	137	.caslat_x = 0x1e << 4, /* 5,6,7,8 */
	138	.taa_ps = 13125,
	139	.twr_ps = 15000,
	140	.trcd_ps = 13125,
	141	.trrd_ps = 7500,
	142	.trp_ps = 13125,
	143	.tras_ps = 37500,
	144	.trc_ps = 50625,
	145	.trfc_ps = 160000,
	146	.twtr_ps = 7500,
	147	.trtp_ps = 7500,
41d91011	148	.refresh_rate_ps = 7800000,
0dd38a35	149	.tfaw_ps = 37500,
41d91011 PK	150	};
	151
	152	int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
	153	unsigned int controller_number,
	154	unsigned int dimm_number)
	155	{
	156	const char dimm_model[] = "Fixed DDR on board";
	157
	158	if ((controller_number == 0) && (dimm_number == 0)) {
	159	memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
	160	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	161	memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
	162	}
	163
	164	return 0;
	165	}
	166
	167	void fsl_ddr_board_options(memctl_options_t *popts,
	168	dimm_params_t *pdimm,
	169	unsigned int ctrl_num)
	170	{
	171	int i;
	172	popts->clk_adjust = 6;
	173	popts->cpo_override = 0x1f;
	174	popts->write_data_delay = 2;
	175	popts->half_strength_driver_enable = 1;
	176	/* Write leveling override */
	177	popts->wrlvl_en = 1;
	178	popts->wrlvl_override = 1;
	179	popts->wrlvl_sample = 0xf;
	180	popts->wrlvl_start = 0x8;
	181	popts->trwt_override = 1;
	182	popts->trwt = 0;
	183
	184	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
	185	popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
	186	popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
	187	}
	188	}
	189
	190	#endif /* CONFIG_SYS_DDR_RAW_TIMING */