]>
Commit | Line | Data |
---|---|---|
03f5c550 | 1 | /* |
568336ec | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
03f5c550 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
03f5c550 WD |
5 | */ |
6 | ||
7 | ||
8 | #include <common.h> | |
9 | ||
10 | ||
11 | /* | |
12 | * CADMUS Board System Registers | |
13 | */ | |
6d0f6bcf JCPV |
14 | #ifndef CONFIG_SYS_CADMUS_BASE_REG |
15 | #define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) | |
03f5c550 WD |
16 | #endif |
17 | ||
18 | typedef struct cadmus_reg { | |
19 | u_char cm_ver; /* Board version */ | |
20 | u_char cm_csr; /* General control/status */ | |
21 | u_char cm_rst; /* Reset control */ | |
22 | u_char cm_hsclk; /* High speed clock */ | |
23 | u_char cm_hsxclk; /* High speed clock extended */ | |
24 | u_char cm_led; /* LED data */ | |
25 | u_char cm_pci; /* PCI control/status */ | |
26 | u_char cm_dma; /* DMA control */ | |
27 | u_char cm_reserved[248]; /* Total 256 bytes */ | |
28 | } cadmus_reg_t; | |
29 | ||
30 | ||
31 | unsigned int | |
32 | get_board_version(void) | |
33 | { | |
6d0f6bcf | 34 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; |
03f5c550 WD |
35 | |
36 | return cadmus->cm_ver; | |
37 | } | |
38 | ||
39 | ||
40 | unsigned long | |
41 | get_clock_freq(void) | |
42 | { | |
6d0f6bcf | 43 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; |
03f5c550 WD |
44 | |
45 | uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ | |
46 | ||
47 | if (pci1_speed == 0) { | |
568336ec | 48 | return 33333333; |
03f5c550 | 49 | } else if (pci1_speed == 1) { |
568336ec | 50 | return 66666666; |
03f5c550 WD |
51 | } else { |
52 | /* Really, unknown. Be safe? */ | |
568336ec | 53 | return 33333333; |
03f5c550 WD |
54 | } |
55 | } | |
56 | ||
57 | ||
58 | unsigned int | |
59 | get_pci_slot(void) | |
60 | { | |
6d0f6bcf | 61 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; |
03f5c550 WD |
62 | |
63 | /* | |
64 | * PCI slot in USER bits CSR[6:7] by convention. | |
65 | */ | |
66 | return ((cadmus->cm_csr >> 6) & 0x3) + 1; | |
67 | } | |
68 | ||
69 | ||
70 | unsigned int | |
71 | get_pci_dual(void) | |
72 | { | |
6d0f6bcf | 73 | volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; |
03f5c550 WD |
74 | |
75 | /* | |
76 | * PCI DUAL in CM_PCI[3] | |
77 | */ | |
78 | return cadmus->cm_pci & 0x10; | |
79 | } |