]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/freescale/common/cadmus.c
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / board / freescale / common / cadmus.c
CommitLineData
03f5c550
WD
1/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23
24#include <common.h>
25
26
27/*
28 * CADMUS Board System Registers
29 */
6d0f6bcf
JCPV
30#ifndef CONFIG_SYS_CADMUS_BASE_REG
31#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
03f5c550
WD
32#endif
33
34typedef struct cadmus_reg {
35 u_char cm_ver; /* Board version */
36 u_char cm_csr; /* General control/status */
37 u_char cm_rst; /* Reset control */
38 u_char cm_hsclk; /* High speed clock */
39 u_char cm_hsxclk; /* High speed clock extended */
40 u_char cm_led; /* LED data */
41 u_char cm_pci; /* PCI control/status */
42 u_char cm_dma; /* DMA control */
43 u_char cm_reserved[248]; /* Total 256 bytes */
44} cadmus_reg_t;
45
46
47unsigned int
48get_board_version(void)
49{
6d0f6bcf 50 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
03f5c550
WD
51
52 return cadmus->cm_ver;
53}
54
55
56unsigned long
57get_clock_freq(void)
58{
6d0f6bcf 59 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
03f5c550
WD
60
61 uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
62
63 if (pci1_speed == 0) {
64 return 33000000;
65 } else if (pci1_speed == 1) {
66 return 66000000;
67 } else {
68 /* Really, unknown. Be safe? */
69 return 33000000;
70 }
71}
72
73
74unsigned int
75get_pci_slot(void)
76{
6d0f6bcf 77 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
03f5c550
WD
78
79 /*
80 * PCI slot in USER bits CSR[6:7] by convention.
81 */
82 return ((cadmus->cm_csr >> 6) & 0x3) + 1;
83}
84
85
86unsigned int
87get_pci_dual(void)
88{
6d0f6bcf 89 volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
03f5c550
WD
90
91 /*
92 * PCI DUAL in CM_PCI[3]
93 */
94 return cadmus->cm_pci & 0x10;
95}