[thirdparty/u-boot.git] / board / freescale / common / pixis.c

/*
 * Copyright 2006,2010 Freescale Semiconductor
 * Jeff Brown
 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <asm/io.h>

#define pixis_base (u8 *)PIXIS_BASE

/*
 * Simple board reset.
 */
void pixis_reset(void)
{
	out_8(pixis_base + PIXIS_RST, 0);

	while (1);
}

/*
 * Per table 27, page 58 of MPC8641HPCN spec.
 */
static int set_px_sysclk(unsigned long sysclk)
{
	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;

	switch (sysclk) {
	case 33:
		sysclk_s = 0x04;
		sysclk_r = 0x04;
		sysclk_v = 0x07;
		sysclk_aux = 0x00;
		break;
	case 40:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x20;
		sysclk_aux = 0x01;
		break;
	case 50:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x2A;
		sysclk_aux = 0x02;
		break;
	case 66:
		sysclk_s = 0x01;
		sysclk_r = 0x04;
		sysclk_v = 0x04;
		sysclk_aux = 0x03;
		break;
	case 83:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x04;
		break;
	case 100:
		sysclk_s = 0x01;
		sysclk_r = 0x1F;
		sysclk_v = 0x5C;
		sysclk_aux = 0x05;
		break;
	case 134:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x3B;
		sysclk_aux = 0x06;
		break;
	case 166:
		sysclk_s = 0x06;
		sysclk_r = 0x1F;
		sysclk_v = 0x4B;
		sysclk_aux = 0x07;
		break;
	default:
		printf("Unsupported SYSCLK frequency.\n");
		return 0;
	}

	vclkh = (sysclk_s << 5) | sysclk_r;
	vclkl = sysclk_v;

	out_8(pixis_base + PIXIS_VCLKH, vclkh);
	out_8(pixis_base + PIXIS_VCLKL, vclkl);

	out_8(pixis_base + PIXIS_AUX, sysclk_aux);

	return 1;
}

/* Set the CFG_SYSPLL bits
 *
 * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
 * read_from_px_regs() is called.
 */
static int set_px_mpxpll(unsigned long mpxpll)
{
	switch (mpxpll) {
	case 2:
	case 4:
	case 6:
	case 8:
	case 10:
	case 12:
	case 14:
	case 16:
		clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
		return 1;
	}

	printf("Unsupported MPXPLL ratio.\n");
	return 0;
}

static int set_px_corepll(unsigned long corepll)
{
	u8 val;

	switch (corepll) {
	case 20:
		val = 0x08;
		break;
	case 25:
		val = 0x0C;
		break;
	case 30:
		val = 0x10;
		break;
	case 35:
		val = 0x1C;
		break;
	case 40:
		val = 0x14;
		break;
	case 45:
		val = 0x0E;
		break;
	default:
		printf("Unsupported COREPLL ratio.\n");
		return 0;
	}

	clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
	return 1;
}

#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE		0x1C
#endif

/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
 *
 * The PIXIS can be programmed to look at either the on-board dip switches
 * or various other PIXIS registers to determine the values for COREPLL,
 * MPXPLL, and SYSCLK.
 *
 * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
 * register that tells the pixis to use the various PIXIS register.
 */
static void read_from_px_regs(int set)
{
	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);

	if (set)
		tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
	else
		tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;

	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}

/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
 * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
 */
#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
#define CONFIG_SYS_PIXIS_VBOOT_ENABLE	0x04
#endif

/* Configure the source of the boot location
 *
 * The PIXIS can be programmed to look at either the on-board dip switches
 * or the PX_VBOOT[LBMAP] register to determine where we should boot.
 *
 * If we want to boot from the alternate boot bank, we need to tell the PIXIS
 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
 */
static void read_from_px_regs_altbank(int set)
{
	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);

	if (set)
		tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
	else
		tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;

	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}

/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
 * tells the PIXIS what the alternate flash bank is.
 *
 * Note that it's not really a mask.  It contains the actual LBMAP bits that
 * must be set to select the alternate bank.  This code assumes that the
 * primary bank has these bits set to 0, and the alternate bank has these
 * bits set to 1.
 */
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
#endif

/* Tell the PIXIS to boot from the default flash bank
 *
 * Program the default flash bank into the VBOOT register.  This register is
 * used only if PX_VCFGEN1[FLASH]=1.
 */
static void clear_altbank(void)
{
	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}

/* Tell the PIXIS to boot from the alternate flash bank
 *
 * Program the alternate flash bank into the VBOOT register.  This register is
 * used only if PX_VCFGEN1[FLASH]=1.
 */
static void set_altbank(void)
{
	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}

/* Reset the board with watchdog disabled.
 *
 * This respects the altbank setting.
 */
static void set_px_go(void)
{
	/* Disable the VELA sequencer and watchdog */
	clrbits_8(pixis_base + PIXIS_VCTL, 9);

	/* Reboot by starting the VELA sequencer */
	setbits_8(pixis_base + PIXIS_VCTL, 0x1);

	while (1);
}

/* Reset the board with watchdog enabled.
 *
 * This respects the altbank setting.
 */
static void set_px_go_with_watchdog(void)
{
	/* Disable the VELA sequencer */
	clrbits_8(pixis_base + PIXIS_VCTL, 1);

	/* Enable the watchdog and reboot by starting the VELA sequencer */
	setbits_8(pixis_base + PIXIS_VCTL, 0x9);

	while (1);
}

/* Disable the watchdog
 *
 */
static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
				      char * const argv[])
{
	/* Disable the VELA sequencer and the watchdog */
	clrbits_8(pixis_base + PIXIS_VCTL, 9);

	return 0;
}

U_BOOT_CMD(
	diswd, 1, 0, pixis_disable_watchdog_cmd,
	"Disable watchdog timer",
	""
);

#ifdef CONFIG_PIXIS_SGMII_CMD

/* Enable or disable SGMII mode for a TSEC
 */
static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int which_tsec = -1;
	unsigned char mask;
	unsigned char switch_mask;

	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
		which_tsec = simple_strtoul(argv[1], NULL, 0);

	switch (which_tsec) {
#ifdef CONFIG_TSEC1
	case 1:
		mask = PIXIS_VSPEED2_TSEC1SER;
		switch_mask = PIXIS_VCFGEN1_TSEC1SER;
		break;
#endif
#ifdef CONFIG_TSEC2
	case 2:
		mask = PIXIS_VSPEED2_TSEC2SER;
		switch_mask = PIXIS_VCFGEN1_TSEC2SER;
		break;
#endif
#ifdef CONFIG_TSEC3
	case 3:
		mask = PIXIS_VSPEED2_TSEC3SER;
		switch_mask = PIXIS_VCFGEN1_TSEC3SER;
		break;
#endif
#ifdef CONFIG_TSEC4
	case 4:
		mask = PIXIS_VSPEED2_TSEC4SER;
		switch_mask = PIXIS_VCFGEN1_TSEC4SER;
		break;
#endif
	default:
		mask = PIXIS_VSPEED2_MASK;
		switch_mask = PIXIS_VCFGEN1_MASK;
		break;
	}

	/* Toggle whether the switches or FPGA control the settings */
	if (!strcmp(argv[argc - 1], "switch"))
		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
	else
		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);

	/* If it's not the switches, enable or disable SGMII, as specified */
	if (!strcmp(argv[argc - 1], "on"))
		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
	else if (!strcmp(argv[argc - 1], "off"))
		setbits_8(pixis_base + PIXIS_VSPEED2, mask);

	return 0;
}

U_BOOT_CMD(
	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
	"pixis_set_sgmii"
	" - Enable or disable SGMII mode for a given TSEC \n",
	"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
	"    TSEC num: 1,2,3,4 or 'all'.  'all' is default.\n"
	"    on - enables SGMII\n"
	"    off - disables SGMII\n"
	"    switch - use switch settings"
);

#endif

/*
 * This function takes the non-integral cpu:mpx pll ratio
 * and converts it to an integer that can be used to assign
 * FPGA register values.
 * input: strptr i.e. argv[2]
 */
static unsigned long strfractoint(char *strptr)
{
	int i, j;
	int mulconst;
	int no_dec = 0;
	unsigned long intval = 0, decval = 0;
	char intarr[3], decarr[3];

	/* Assign the integer part to intarr[]
	 * If there is no decimal point i.e.
	 * if the ratio is an integral value
	 * simply create the intarr.
	 */
	i = 0;
	while (strptr[i] != '.') {
		if (strptr[i] == 0) {
			no_dec = 1;
			break;
		}
		intarr[i] = strptr[i];
		i++;
	}

	intarr[i] = '\0';

	if (no_dec) {
		/* Currently needed only for single digit corepll ratios */
		mulconst = 10;
		decval = 0;
	} else {
		j = 0;
		i++;		/* Skipping the decimal point */
		while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
			decarr[j] = strptr[i];
			i++;
			j++;
		}

		decarr[j] = '\0';

		mulconst = 1;
		for (i = 0; i < j; i++)
			mulconst *= 10;
		decval = simple_strtoul(decarr, NULL, 10);
	}

	intval = simple_strtoul(intarr, NULL, 10);
	intval = intval * mulconst;

	return intval + decval;
}

static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	unsigned int i;
	char *p_cf = NULL;
	char *p_cf_sysclk = NULL;
	char *p_cf_corepll = NULL;
	char *p_cf_mpxpll = NULL;
	char *p_altbank = NULL;
	char *p_wd = NULL;
	int unknown_param = 0;

	/*
	 * No args is a simple reset request.
	 */
	if (argc <= 1) {
		pixis_reset();
		/* not reached */
	}

	for (i = 1; i < argc; i++) {
		if (strcmp(argv[i], "cf") == 0) {
			p_cf = argv[i];
			if (i + 3 >= argc) {
				break;
			}
			p_cf_sysclk = argv[i+1];
			p_cf_corepll = argv[i+2];
			p_cf_mpxpll = argv[i+3];
			i += 3;
			continue;
		}

		if (strcmp(argv[i], "altbank") == 0) {
			p_altbank = argv[i];
			continue;
		}

		if (strcmp(argv[i], "wd") == 0) {
			p_wd = argv[i];
			continue;
		}

		unknown_param = 1;
	}

	/*
	 * Check that cf has all required parms
	 */
	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
	    ||	unknown_param) {
#ifdef CONFIG_SYS_LONGHELP
		puts(cmdtp->help);
		putc('\n');
#endif
		return 1;
	}

	/*
	 * PIXIS seems to be sensitive to the ordering of
	 * the registers that are touched.
	 */
	read_from_px_regs(0);

	if (p_altbank)
		read_from_px_regs_altbank(0);

	clear_altbank();

	/*
	 * Clock configuration specified.
	 */
	if (p_cf) {
		unsigned long sysclk;
		unsigned long corepll;
		unsigned long mpxpll;

		sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
		corepll = strfractoint(p_cf_corepll);
		mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);

		if (!(set_px_sysclk(sysclk)
		      && set_px_corepll(corepll)
		      && set_px_mpxpll(mpxpll))) {
#ifdef CONFIG_SYS_LONGHELP
			puts(cmdtp->help);
			putc('\n');
#endif
			return 1;
		}
		read_from_px_regs(1);
	}

	/*
	 * Altbank specified
	 *
	 * NOTE CHANGE IN BEHAVIOR: previous code would default
	 * to enabling watchdog if altbank is specified.
	 * Now the watchdog must be enabled explicitly using 'wd'.
	 */
	if (p_altbank) {
		set_altbank();
		read_from_px_regs_altbank(1);
	}

	/*
	 * Reset with watchdog specified.
	 */
	if (p_wd)
		set_px_go_with_watchdog();
	else
		set_px_go();

	/*
	 * Shouldn't be reached.
	 */
	return 0;
}


U_BOOT_CMD(
	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
	"Reset the board using the FPGA sequencer",
	"    pixis_reset\n"
	"    pixis_reset [altbank]\n"
	"    pixis_reset altbank wd\n"
	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
);
Commit	Line	Data
126aa70f	1	/*
2feb4af0	2	* Copyright 2006,2010 Freescale Semiconductor
126aa70f JL	3	* Jeff Brown
	4	* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
126aa70f JL	7	*/
	8
	9	#include <common.h>
126aa70f	10	#include <command.h>
5a8a163a	11	#include <asm/io.h>
ad8f8687	12
2feb4af0	13	#define pixis_base (u8 *)PIXIS_BASE
3d98b858 HW	14
	15	/*
	16	* Simple board reset.
	17	*/
	18	void pixis_reset(void)
	19	{
048e7efe	20	out_8(pixis_base + PIXIS_RST, 0);
3d98b858	21
2feb4af0 TT	22	while (1);
2feb4af0 TT	23	}
3d98b858	24
126aa70f JL	25	/*
	26	* Per table 27, page 58 of MPC8641HPCN spec.
	27	*/
2feb4af0	28	static int set_px_sysclk(unsigned long sysclk)
126aa70f JL	29	{
	30	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
	31
	32	switch (sysclk) {
	33	case 33:
	34	sysclk_s = 0x04;
	35	sysclk_r = 0x04;
	36	sysclk_v = 0x07;
	37	sysclk_aux = 0x00;
	38	break;
	39	case 40:
	40	sysclk_s = 0x01;
	41	sysclk_r = 0x1F;
	42	sysclk_v = 0x20;
	43	sysclk_aux = 0x01;
	44	break;
	45	case 50:
	46	sysclk_s = 0x01;
	47	sysclk_r = 0x1F;
	48	sysclk_v = 0x2A;
	49	sysclk_aux = 0x02;
	50	break;
	51	case 66:
	52	sysclk_s = 0x01;
	53	sysclk_r = 0x04;
	54	sysclk_v = 0x04;
	55	sysclk_aux = 0x03;
	56	break;
	57	case 83:
	58	sysclk_s = 0x01;
	59	sysclk_r = 0x1F;
	60	sysclk_v = 0x4B;
	61	sysclk_aux = 0x04;
	62	break;
	63	case 100:
	64	sysclk_s = 0x01;
	65	sysclk_r = 0x1F;
	66	sysclk_v = 0x5C;
	67	sysclk_aux = 0x05;
	68	break;
	69	case 134:
	70	sysclk_s = 0x06;
	71	sysclk_r = 0x1F;
	72	sysclk_v = 0x3B;
	73	sysclk_aux = 0x06;
	74	break;
	75	case 166:
	76	sysclk_s = 0x06;
	77	sysclk_r = 0x1F;
	78	sysclk_v = 0x4B;
	79	sysclk_aux = 0x07;
	80	break;
	81	default:
	82	printf("Unsupported SYSCLK frequency.\n");
	83	return 0;
	84	}
	85
80e955c7	86	vclkh = (sysclk_s << 5) \| sysclk_r;
126aa70f JL	87	vclkl = sysclk_v;
126aa70f JL	88
048e7efe KG	89	out_8(pixis_base + PIXIS_VCLKH, vclkh);
048e7efe KG	90	out_8(pixis_base + PIXIS_VCLKL, vclkl);
126aa70f	91
048e7efe	92	out_8(pixis_base + PIXIS_AUX, sysclk_aux);
126aa70f JL	93
	94	return 1;
	95	}
	96
2feb4af0 TT	97	/* Set the CFG_SYSPLL bits
	98	*
	99	* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
	100	* read_from_px_regs() is called.
	101	*/
	102	static int set_px_mpxpll(unsigned long mpxpll)
126aa70f	103	{
126aa70f JL	104	switch (mpxpll) {
	105	case 2:
	106	case 4:
	107	case 6:
	108	case 8:
	109	case 10:
	110	case 12:
	111	case 14:
	112	case 16:
2feb4af0 TT	113	clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
2feb4af0 TT	114	return 1;
126aa70f JL	115	}
126aa70f JL	116
2feb4af0 TT	117	printf("Unsupported MPXPLL ratio.\n");
2feb4af0 TT	118	return 0;
126aa70f JL	119	}
126aa70f JL	120
2feb4af0	121	static int set_px_corepll(unsigned long corepll)
126aa70f	122	{
126aa70f JL	123	u8 val;
126aa70f JL	124
2feb4af0	125	switch (corepll) {
126aa70f JL	126	case 20:
	127	val = 0x08;
	128	break;
	129	case 25:
	130	val = 0x0C;
	131	break;
	132	case 30:
	133	val = 0x10;
	134	break;
	135	case 35:
	136	val = 0x1C;
	137	break;
	138	case 40:
	139	val = 0x14;
	140	break;
	141	case 45:
	142	val = 0x0E;
	143	break;
	144	default:
	145	printf("Unsupported COREPLL ratio.\n");
	146	return 0;
	147	}
	148
2feb4af0	149	clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
126aa70f JL	150	return 1;
	151	}
	152
2feb4af0 TT	153	#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
	154	#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
	155	#endif
126aa70f	156
2feb4af0 TT	157	/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
	158	*
	159	* The PIXIS can be programmed to look at either the on-board dip switches
	160	* or various other PIXIS registers to determine the values for COREPLL,
	161	* MPXPLL, and SYSCLK.
	162	*
	163	* CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
	164	* register that tells the pixis to use the various PIXIS register.
	165	*/
	166	static void read_from_px_regs(int set)
126aa70f	167	{
048e7efe	168	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
126aa70f JL	169
126aa70f JL	170	if (set)
2feb4af0	171	tmp = tmp \| CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
126aa70f	172	else
2feb4af0 TT	173	tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
2feb4af0 TT	174
048e7efe	175	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
126aa70f JL	176	}
126aa70f JL	177
2feb4af0 TT	178	/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
	179	* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
	180	*/
	181	#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
	182	#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
	183	#endif
126aa70f	184
2feb4af0 TT	185	/* Configure the source of the boot location
	186	*
	187	* The PIXIS can be programmed to look at either the on-board dip switches
	188	* or the PX_VBOOT[LBMAP] register to determine where we should boot.
	189	*
	190	* If we want to boot from the alternate boot bank, we need to tell the PIXIS
	191	* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
	192	*/
	193	static void read_from_px_regs_altbank(int set)
126aa70f	194	{
048e7efe	195	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
126aa70f JL	196
126aa70f JL	197	if (set)
2feb4af0	198	tmp = tmp \| CONFIG_SYS_PIXIS_VBOOT_ENABLE;
126aa70f	199	else
2feb4af0 TT	200	tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
2feb4af0 TT	201
048e7efe	202	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
126aa70f JL	203	}
126aa70f JL	204
2feb4af0 TT	205	/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
	206	* tells the PIXIS what the alternate flash bank is.
	207	*
	208	* Note that it's not really a mask. It contains the actual LBMAP bits that
	209	* must be set to select the alternate bank. This code assumes that the
	210	* primary bank has these bits set to 0, and the alternate bank has these
	211	* bits set to 1.
	212	*/
6d0f6bcf JCPV	213	#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
6d0f6bcf JCPV	214	#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
db74b3c1	215	#endif
126aa70f	216
2feb4af0 TT	217	/* Tell the PIXIS to boot from the default flash bank
	218	*
	219	* Program the default flash bank into the VBOOT register. This register is
	220	* used only if PX_VCFGEN1[FLASH]=1.
	221	*/
	222	static void clear_altbank(void)
16c3cde0	223	{
2feb4af0	224	clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
16c3cde0 JY	225	}
16c3cde0 JY	226
2feb4af0 TT	227	/* Tell the PIXIS to boot from the alternate flash bank
	228	*
	229	* Program the alternate flash bank into the VBOOT register. This register is
	230	* used only if PX_VCFGEN1[FLASH]=1.
	231	*/
	232	static void set_altbank(void)
126aa70f	233	{
2feb4af0	234	setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
126aa70f JL	235	}
126aa70f JL	236
2feb4af0 TT	237	/* Reset the board with watchdog disabled.
	238	*
	239	* This respects the altbank setting.
	240	*/
	241	static void set_px_go(void)
126aa70f	242	{
2feb4af0 TT	243	/* Disable the VELA sequencer and watchdog */
2feb4af0 TT	244	clrbits_8(pixis_base + PIXIS_VCTL, 9);
126aa70f	245
2feb4af0 TT	246	/* Reboot by starting the VELA sequencer */
2feb4af0 TT	247	setbits_8(pixis_base + PIXIS_VCTL, 0x1);
126aa70f	248
2feb4af0	249	while (1);
126aa70f JL	250	}
126aa70f JL	251
2feb4af0 TT	252	/* Reset the board with watchdog enabled.
	253	*
	254	* This respects the altbank setting.
	255	*/
	256	static void set_px_go_with_watchdog(void)
126aa70f	257	{
2feb4af0 TT	258	/* Disable the VELA sequencer */
2feb4af0 TT	259	clrbits_8(pixis_base + PIXIS_VCTL, 1);
126aa70f	260
2feb4af0 TT	261	/* Enable the watchdog and reboot by starting the VELA sequencer */
2feb4af0 TT	262	setbits_8(pixis_base + PIXIS_VCTL, 0x9);
126aa70f	263
2feb4af0	264	while (1);
126aa70f JL	265	}
126aa70f JL	266
2feb4af0 TT	267	/* Disable the watchdog
	268	*
	269	*/
	270	static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
54841ab5	271	char * const argv[])
126aa70f	272	{
2feb4af0 TT	273	/* Disable the VELA sequencer and the watchdog */
2feb4af0 TT	274	clrbits_8(pixis_base + PIXIS_VCTL, 9);
126aa70f JL	275
	276	return 0;
	277	}
	278
126aa70f	279	U_BOOT_CMD(
a89c33db WD	280	diswd, 1, 0, pixis_disable_watchdog_cmd,
	281	"Disable watchdog timer",
	282	""
	283	);
126aa70f	284
bff188ba	285	#ifdef CONFIG_PIXIS_SGMII_CMD
2feb4af0 TT	286
	287	/* Enable or disable SGMII mode for a TSEC
	288	*/
54841ab5	289	static int pixis_set_sgmii(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
5a8a163a AF	290	{
5a8a163a AF	291	int which_tsec = -1;
2feb4af0 TT	292	unsigned char mask;
2feb4af0 TT	293	unsigned char switch_mask;
5a8a163a	294
2feb4af0 TT	295	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
2feb4af0 TT	296	which_tsec = simple_strtoul(argv[1], NULL, 0);
5a8a163a AF	297
5a8a163a AF	298	switch (which_tsec) {
bff188ba	299	#ifdef CONFIG_TSEC1
5a8a163a AF	300	case 1:
	301	mask = PIXIS_VSPEED2_TSEC1SER;
	302	switch_mask = PIXIS_VCFGEN1_TSEC1SER;
	303	break;
bff188ba LY	304	#endif
	305	#ifdef CONFIG_TSEC2
	306	case 2:
	307	mask = PIXIS_VSPEED2_TSEC2SER;
	308	switch_mask = PIXIS_VCFGEN1_TSEC2SER;
	309	break;
	310	#endif
	311	#ifdef CONFIG_TSEC3
5a8a163a AF	312	case 3:
	313	mask = PIXIS_VSPEED2_TSEC3SER;
	314	switch_mask = PIXIS_VCFGEN1_TSEC3SER;
	315	break;
bff188ba LY	316	#endif
	317	#ifdef CONFIG_TSEC4
	318	case 4:
	319	mask = PIXIS_VSPEED2_TSEC4SER;
	320	switch_mask = PIXIS_VCFGEN1_TSEC4SER;
	321	break;
	322	#endif
5a8a163a	323	default:
bff188ba LY	324	mask = PIXIS_VSPEED2_MASK;
bff188ba LY	325	switch_mask = PIXIS_VCFGEN1_MASK;
5a8a163a AF	326	break;
	327	}
	328
	329	/* Toggle whether the switches or FPGA control the settings */
	330	if (!strcmp(argv[argc - 1], "switch"))
048e7efe	331	clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
5a8a163a	332	else
048e7efe	333	setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
5a8a163a AF	334
	335	/* If it's not the switches, enable or disable SGMII, as specified */
	336	if (!strcmp(argv[argc - 1], "on"))
048e7efe	337	clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
5a8a163a	338	else if (!strcmp(argv[argc - 1], "off"))
048e7efe	339	setbits_8(pixis_base + PIXIS_VSPEED2, mask);
5a8a163a AF	340
	341	return 0;
	342	}
	343
	344	U_BOOT_CMD(
a89c33db WD	345	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
	346	"pixis_set_sgmii"
	347	" - Enable or disable SGMII mode for a given TSEC \n",
	348	"\npixis_set_sgmii [TSEC num] <on\|off\|switch>\n"
	349	" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
	350	" on - enables SGMII\n"
	351	" off - disables SGMII\n"
	352	" switch - use switch settings"
	353	);
2feb4af0	354
5a8a163a AF	355	#endif
5a8a163a AF	356
126aa70f JL	357	/*
	358	* This function takes the non-integral cpu:mpx pll ratio
	359	* and converts it to an integer that can be used to assign
	360	* FPGA register values.
	361	* input: strptr i.e. argv[2]
	362	*/
2feb4af0	363	static unsigned long strfractoint(char *strptr)
126aa70f	364	{
2feb4af0	365	int i, j;
126aa70f	366	int mulconst;
8dbd4b74	367	int no_dec = 0;
2feb4af0 TT	368	unsigned long intval = 0, decval = 0;
2feb4af0 TT	369	char intarr[3], decarr[3];
126aa70f JL	370
	371	/* Assign the integer part to intarr[]
	372	* If there is no decimal point i.e.
	373	* if the ratio is an integral value
	374	* simply create the intarr.
	375	*/
	376	i = 0;
16c3cde0	377	while (strptr[i] != '.') {
126aa70f JL	378	if (strptr[i] == 0) {
	379	no_dec = 1;
	380	break;
	381	}
	382	intarr[i] = strptr[i];
	383	i++;
	384	}
	385
126aa70f JL	386	intarr[i] = '\0';
	387
	388	if (no_dec) {
	389	/* Currently needed only for single digit corepll ratios */
80e955c7	390	mulconst = 10;
126aa70f JL	391	decval = 0;
	392	} else {
	393	j = 0;
80e955c7	394	i++; /* Skipping the decimal point */
16c3cde0	395	while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
126aa70f JL	396	decarr[j] = strptr[i];
	397	i++;
	398	j++;
	399	}
	400
126aa70f JL	401	decarr[j] = '\0';
	402
	403	mulconst = 1;
2feb4af0	404	for (i = 0; i < j; i++)
126aa70f	405	mulconst *= 10;
2feb4af0	406	decval = simple_strtoul(decarr, NULL, 10);
126aa70f JL	407	}
126aa70f JL	408
2feb4af0	409	intval = simple_strtoul(intarr, NULL, 10);
126aa70f JL	410	intval = intval * mulconst;
126aa70f JL	411
2feb4af0	412	return intval + decval;
126aa70f	413	}
3d98b858	414
54841ab5	415	static int pixis_reset_cmd(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
3d98b858	416	{
16c3cde0 JY	417	unsigned int i;
	418	char *p_cf = NULL;
	419	char *p_cf_sysclk = NULL;
	420	char *p_cf_corepll = NULL;
	421	char *p_cf_mpxpll = NULL;
	422	char *p_altbank = NULL;
	423	char *p_wd = NULL;
2feb4af0	424	int unknown_param = 0;
3d98b858 HW	425
	426	/*
	427	* No args is a simple reset request.
	428	*/
	429	if (argc <= 1) {
	430	pixis_reset();
	431	/* not reached */
	432	}
	433
16c3cde0 JY	434	for (i = 1; i < argc; i++) {
	435	if (strcmp(argv[i], "cf") == 0) {
	436	p_cf = argv[i];
	437	if (i + 3 >= argc) {
	438	break;
	439	}
	440	p_cf_sysclk = argv[i+1];
	441	p_cf_corepll = argv[i+2];
	442	p_cf_mpxpll = argv[i+3];
	443	i += 3;
	444	continue;
	445	}
3d98b858	446
16c3cde0 JY	447	if (strcmp(argv[i], "altbank") == 0) {
	448	p_altbank = argv[i];
	449	continue;
3d98b858 HW	450	}
3d98b858 HW	451
16c3cde0 JY	452	if (strcmp(argv[i], "wd") == 0) {
	453	p_wd = argv[i];
	454	continue;
3d98b858 HW	455	}
3d98b858 HW	456
16c3cde0 JY	457	unknown_param = 1;
16c3cde0 JY	458	}
3d98b858	459
16c3cde0 JY	460	/*
	461	* Check that cf has all required parms
	462	*/
	463	if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
53677ef1	464	\|\| unknown_param) {
f7fecc3e	465	#ifdef CONFIG_SYS_LONGHELP
16c3cde0	466	puts(cmdtp->help);
5bdeff32	467	putc('\n');
f7fecc3e	468	#endif
16c3cde0 JY	469	return 1;
	470	}
	471
	472	/*
	473	* PIXIS seems to be sensitive to the ordering of
	474	* the registers that are touched.
	475	*/
	476	read_from_px_regs(0);
	477
2feb4af0	478	if (p_altbank)
16c3cde0	479	read_from_px_regs_altbank(0);
2feb4af0	480
16c3cde0 JY	481	clear_altbank();
	482
	483	/*
	484	* Clock configuration specified.
	485	*/
	486	if (p_cf) {
	487	unsigned long sysclk;
	488	unsigned long corepll;
	489	unsigned long mpxpll;
	490
	491	sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
2feb4af0	492	corepll = strfractoint(p_cf_corepll);
16c3cde0 JY	493	mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
	494
	495	if (!(set_px_sysclk(sysclk)
	496	&& set_px_corepll(corepll)
	497	&& set_px_mpxpll(mpxpll))) {
f7fecc3e	498	#ifdef CONFIG_SYS_LONGHELP
16c3cde0	499	puts(cmdtp->help);
5bdeff32	500	putc('\n');
f7fecc3e	501	#endif
3d98b858 HW	502	return 1;
3d98b858 HW	503	}
16c3cde0 JY	504	read_from_px_regs(1);
16c3cde0 JY	505	}
3d98b858	506
16c3cde0 JY	507	/*
	508	* Altbank specified
	509	*
	510	* NOTE CHANGE IN BEHAVIOR: previous code would default
	511	* to enabling watchdog if altbank is specified.
	512	* Now the watchdog must be enabled explicitly using 'wd'.
	513	*/
	514	if (p_altbank) {
	515	set_altbank();
	516	read_from_px_regs_altbank(1);
	517	}
	518
	519	/*
	520	* Reset with watchdog specified.
	521	*/
2feb4af0	522	if (p_wd)
16c3cde0	523	set_px_go_with_watchdog();
2feb4af0	524	else
16c3cde0	525	set_px_go();
3d98b858	526
16c3cde0 JY	527	/*
	528	* Shouldn't be reached.
	529	*/
3d98b858 HW	530	return 0;
	531	}
	532
	533
	534	U_BOOT_CMD(
6d0f6bcf	535	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
2fb2604d	536	"Reset the board using the FPGA sequencer",
3d98b858 HW	537	" pixis_reset\n"
	538	" pixis_reset [altbank]\n"
	539	" pixis_reset altbank wd\n"
	540	" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
a89c33db WD	541	" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
a89c33db WD	542	);