[thirdparty/u-boot.git] / board / freescale / ls1012aqds / ls1012aqds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
#include <env_internal.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	char buf[64];
	u8 sw;

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);

	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);

	if (sw & QIXIS_LBMAP_ALTBANK)
		printf("flash: 2\n");
	else
		printf("flash: 1\n");

	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());

	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));
	return 0;
}

#ifdef CONFIG_TFABOOT
int dram_init(void)
{
	gd->ram_size = tfa_get_dram_size();
	if (!gd->ram_size)
		gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}
#else
int dram_init(void)
{
	static const struct fsl_mmdc_info mparam = {
		0x05180000,	/* mdctl */
		0x00030035,	/* mdpdc */
		0x12554000,	/* mdotc */
		0xbabf7954,	/* mdcfg0 */
		0xdb328f64,	/* mdcfg1 */
		0x01ff00db,	/* mdcfg2 */
		0x00001680,	/* mdmisc */
		0x0f3c8000,	/* mdref */
		0x00002000,	/* mdrwd */
		0x00bf1023,	/* mdor */
		0x0000003f,	/* mdasp */
		0x0000022a,	/* mpodtctrl */
		0xa1390003,	/* mpzqhwctrl */
	};

	mmdc_init(&mparam);
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
	/* This will break-before-make MMU for DDR */
	update_early_mmu_table();
#endif

	return 0;
}
#endif

int board_early_init_f(void)
{
	fsl_lsch2_early_init_f();

	return 0;
}

#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
	u8 mux_sdhc_cd = 0x80;
	int bus_num = 0;

#ifdef CONFIG_DM_I2C
	struct udevice *dev;
	int ret;

	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
				      1, &dev);
	if (ret) {
		printf("%s: Cannot find udev for a bus %d\n", __func__,
		       bus_num);
		return ret;
	}
	dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
#else
	i2c_set_bus_num(bus_num);

	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
#endif

	return 0;
}
#endif

int board_init(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
				   CONFIG_SYS_CCI400_OFFSET);

	/* Set CCI-400 control override register to enable barrier
	 * transaction */
	if (current_el() == 3)
		out_le32(&cci->ctrl_ord,
			 CCI400_CTRLORD_EN_BARRIER);

#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	erratum_a010315();
#endif

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif
	return 0;
}

int esdhc_status_fixup(void *blob, const char *compat)
{
	char esdhc0_path[] = "/soc/esdhc@1560000";
	char esdhc1_path[] = "/soc/esdhc@1580000";
	u8 card_id;

	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
			 sizeof("okay"), 1);

	/*
	 * The Presence Detect 2 register detects the installation
	 * of cards in various PCI Express or SGMII slots.
	 *
	 * STAT_PRS2[7:5]: Specifies the type of card installed in the
	 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
	 */
	card_id = (QIXIS_READ(present2) & 0xe0) >> 5;

	/* If no adapter is installed in SDHC2, disable SDHC2 */
	if (card_id == 0x7)
		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
				 sizeof("disabled"), 1);
	else
		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
				 sizeof("okay"), 1);
	return 0;
}

static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
			      char *enet_path, char *mdio_path)
{
	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
			 &prop_val.busid, PFE_PROP_LEN, 1);
	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
			 &prop_val.phyid, PFE_PROP_LEN, 1);
	do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
			 &prop_val.mux_val, PFE_PROP_LEN, 1);
	do_fixup_by_path(set_blob, enet_path, "phy-mode",
			 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
	do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
			 &prop_val.phy_mask, PFE_PROP_LEN, 1);
	return 0;
}

static void fdt_fsl_fixup_of_pfe(void *blob)
{
	int i = 0;
	struct pfe_prop_val prop_val;
	void *l_blob = blob;

	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
		FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;

	for (i = 0; i < NUM_ETH_NODE; i++) {
		switch (srds_s1) {
		case SERDES_1_G_PROTOCOL:
			if (i == 0) {
				prop_val.busid = cpu_to_fdt32(
						ETH_1_1G_BUS_ID);
				prop_val.phyid = cpu_to_fdt32(
						ETH_1_1G_PHY_ID);
				prop_val.mux_val = cpu_to_fdt32(
						ETH_1_1G_MDIO_MUX);
				prop_val.phy_mask = cpu_to_fdt32(
						ETH_1G_MDIO_PHY_MASK);
				prop_val.phy_mode = "sgmii";
				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
						   ETH_1_MDIO);
			} else {
				prop_val.busid = cpu_to_fdt32(
						ETH_2_1G_BUS_ID);
				prop_val.phyid = cpu_to_fdt32(
						ETH_2_1G_PHY_ID);
				prop_val.mux_val = cpu_to_fdt32(
						ETH_2_1G_MDIO_MUX);
				prop_val.phy_mask = cpu_to_fdt32(
						ETH_1G_MDIO_PHY_MASK);
				prop_val.phy_mode = "rgmii";
				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
						   ETH_2_MDIO);
			}
		break;
		case SERDES_2_5_G_PROTOCOL:
			if (i == 0) {
				prop_val.busid = cpu_to_fdt32(
						ETH_1_2_5G_BUS_ID);
				prop_val.phyid = cpu_to_fdt32(
						ETH_1_2_5G_PHY_ID);
				prop_val.mux_val = cpu_to_fdt32(
						ETH_1_2_5G_MDIO_MUX);
				prop_val.phy_mask = cpu_to_fdt32(
						ETH_2_5G_MDIO_PHY_MASK);
				prop_val.phy_mode = "sgmii-2500";
				pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
						   ETH_1_MDIO);
			} else {
				prop_val.busid = cpu_to_fdt32(
						ETH_2_2_5G_BUS_ID);
				prop_val.phyid = cpu_to_fdt32(
						ETH_2_2_5G_PHY_ID);
				prop_val.mux_val = cpu_to_fdt32(
						ETH_2_2_5G_MDIO_MUX);
				prop_val.phy_mask = cpu_to_fdt32(
						ETH_2_5G_MDIO_PHY_MASK);
				prop_val.phy_mode = "sgmii-2500";
				pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
						   ETH_2_MDIO);
			}
		break;
		default:
			printf("serdes:[%d]\n", srds_s1);
		}
	}
}

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	arch_fixup_fdt(blob);

	ft_cpu_setup(blob, bd);
	fdt_fsl_fixup_of_pfe(blob);

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
9d044fcb PK	2	/*
9d044fcb PK	3	* Copyright 2016 Freescale Semiconductor, Inc.
9d044fcb PK	4	*/
	5
	6	#include <common.h>
	7	#include <i2c.h>
	8	#include <fdt_support.h>
90526e9f	9	#include <asm/cache.h>
9d044fcb PK	10	#include <asm/io.h>
	11	#include <asm/arch/clock.h>
	12	#include <asm/arch/fsl_serdes.h>
5b404be6 PK	13	#ifdef CONFIG_FSL_LS_PPA
	14	#include <asm/arch/ppa.h>
	15	#endif
9d044fcb	16	#include <asm/arch/fdt.h>
4961eafc	17	#include <asm/arch/mmu.h>
9d044fcb PK	18	#include <asm/arch/soc.h>
	19	#include <ahci.h>
	20	#include <hwconfig.h>
	21	#include <mmc.h>
f3998fdc	22	#include <env_internal.h>
9d044fcb PK	23	#include <scsi.h>
9d044fcb PK	24	#include <fm_eth.h>
9d044fcb PK	25	#include <fsl_esdhc.h>
	26	#include <fsl_mmdc.h>
	27	#include <spl.h>
	28	#include <netdev.h>
e5141cbe	29	#include <fsl_sec.h>
9d044fcb PK	30	#include "../common/qixis.h"
9d044fcb PK	31	#include "ls1012aqds_qixis.h"
7a8df8ba	32	#include "ls1012aqds_pfe.h"
9d044fcb PK	33
	34	DECLARE_GLOBAL_DATA_PTR;
	35
9d044fcb PK	36	int checkboard(void)
	37	{
	38	char buf[64];
	39	u8 sw;
	40
	41	sw = QIXIS_READ(arch);
	42	printf("Board Arch: V%d, ", sw >> 4);
	43	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	44
	45	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
	46
	47	if (sw & QIXIS_LBMAP_ALTBANK)
	48	printf("flash: 2\n");
	49	else
	50	printf("flash: 1\n");
	51
	52	printf("FPGA: v%d (%s), build %d",
	53	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	54	(int)qixis_read_minor());
	55
	56	/* the timestamp string contains "\n" at the end */
	57	printf(" on %s", qixis_read_time(buf));
	58	return 0;
	59	}
	60
10c8aa16 RB	61	#ifdef CONFIG_TFABOOT
	62	int dram_init(void)
	63	{
	64	gd->ram_size = tfa_get_dram_size();
	65	if (!gd->ram_size)
	66	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	67
	68	return 0;
	69	}
	70	#else
9d044fcb PK	71	int dram_init(void)
9d044fcb PK	72	{
1fdcc8df YS	73	static const struct fsl_mmdc_info mparam = {
	74	0x05180000, /* mdctl */
	75	0x00030035, /* mdpdc */
	76	0x12554000, /* mdotc */
	77	0xbabf7954, /* mdcfg0 */
	78	0xdb328f64, /* mdcfg1 */
	79	0x01ff00db, /* mdcfg2 */
	80	0x00001680, /* mdmisc */
	81	0x0f3c8000, /* mdref */
	82	0x00002000, /* mdrwd */
	83	0x00bf1023, /* mdor */
	84	0x0000003f, /* mdasp */
	85	0x0000022a, /* mpodtctrl */
	86	0xa1390003, /* mpzqhwctrl */
	87	};
	88
	89	mmdc_init(&mparam);
9d044fcb	90	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
4961eafc YS	91	#if !defined(CONFIG_SPL) \|\| defined(CONFIG_SPL_BUILD)
	92	/* This will break-before-make MMU for DDR */
	93	update_early_mmu_table();
	94	#endif
9d044fcb PK	95
	96	return 0;
	97	}
10c8aa16	98	#endif
9d044fcb PK	99
	100	int board_early_init_f(void)
	101	{
	102	fsl_lsch2_early_init_f();
	103
	104	return 0;
	105	}
	106
	107	#ifdef CONFIG_MISC_INIT_R
	108	int misc_init_r(void)
	109	{
	110	u8 mux_sdhc_cd = 0x80;
a0affb36 BL	111	int bus_num = 0;
	112
	113	#ifdef CONFIG_DM_I2C
	114	struct udevice *dev;
	115	int ret;
	116
	117	ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
	118	1, &dev);
	119	if (ret) {
	120	printf("%s: Cannot find udev for a bus %d\n", __func__,
	121	bus_num);
	122	return ret;
	123	}
	124	dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
	125	#else
	126	i2c_set_bus_num(bus_num);
9d044fcb PK	127
9d044fcb PK	128	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
a0affb36 BL	129	#endif
a0affb36 BL	130
9d044fcb PK	131	return 0;
	132	}
	133	#endif
	134
	135	int board_init(void)
	136	{
63b2316c AK	137	struct ccsr_cci400 cci = (struct ccsr_cci400 )(CONFIG_SYS_IMMR +
63b2316c AK	138	CONFIG_SYS_CCI400_OFFSET);
9d044fcb PK	139
	140	/* Set CCI-400 control override register to enable barrier
	141	* transaction */
10c8aa16 RB	142	if (current_el() == 3)
	143	out_le32(&cci->ctrl_ord,
	144	CCI400_CTRLORD_EN_BARRIER);
9d044fcb	145
b392a6d4 HZ	146	#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
	147	erratum_a010315();
	148	#endif
	149
9d044fcb PK	150	#ifdef CONFIG_ENV_IS_NOWHERE
	151	gd->env_addr = (ulong)&default_environment[0];
	152	#endif
5b404be6	153
e5141cbe RB	154	#ifdef CONFIG_FSL_CAAM
	155	sec_init();
	156	#endif
	157
5b404be6 PK	158	#ifdef CONFIG_FSL_LS_PPA
	159	ppa_init();
	160	#endif
9d044fcb PK	161	return 0;
	162	}
	163
208e1ae8 YL	164	int esdhc_status_fixup(void blob, const char compat)
	165	{
	166	char esdhc0_path[] = "/soc/esdhc@1560000";
	167	char esdhc1_path[] = "/soc/esdhc@1580000";
	168	u8 card_id;
	169
	170	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
	171	sizeof("okay"), 1);
	172
	173	/*
	174	* The Presence Detect 2 register detects the installation
	175	* of cards in various PCI Express or SGMII slots.
	176	*
	177	* STAT_PRS2[7:5]: Specifies the type of card installed in the
	178	* SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
	179	*/
	180	card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
	181
	182	/* If no adapter is installed in SDHC2, disable SDHC2 */
	183	if (card_id == 0x7)
	184	do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
	185	sizeof("disabled"), 1);
	186	else
	187	do_fixup_by_path(blob, esdhc1_path, "status", "okay",
	188	sizeof("okay"), 1);
	189	return 0;
	190	}
	191
7a8df8ba CJ	192	static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
	193	char enet_path, char mdio_path)
	194	{
	195	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
	196	&prop_val.busid, PFE_PROP_LEN, 1);
	197	do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
	198	&prop_val.phyid, PFE_PROP_LEN, 1);
	199	do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
	200	&prop_val.mux_val, PFE_PROP_LEN, 1);
	201	do_fixup_by_path(set_blob, enet_path, "phy-mode",
	202	prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
	203	do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
	204	&prop_val.phy_mask, PFE_PROP_LEN, 1);
	205	return 0;
	206	}
	207
	208	static void fdt_fsl_fixup_of_pfe(void *blob)
	209	{
	210	int i = 0;
	211	struct pfe_prop_val prop_val;
	212	void *l_blob = blob;
	213
	214	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
	215	unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
	216	FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
	217	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
	218
	219	for (i = 0; i < NUM_ETH_NODE; i++) {
	220	switch (srds_s1) {
	221	case SERDES_1_G_PROTOCOL:
	222	if (i == 0) {
	223	prop_val.busid = cpu_to_fdt32(
	224	ETH_1_1G_BUS_ID);
	225	prop_val.phyid = cpu_to_fdt32(
	226	ETH_1_1G_PHY_ID);
	227	prop_val.mux_val = cpu_to_fdt32(
	228	ETH_1_1G_MDIO_MUX);
	229	prop_val.phy_mask = cpu_to_fdt32(
	230	ETH_1G_MDIO_PHY_MASK);
	231	prop_val.phy_mode = "sgmii";
	232	pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
	233	ETH_1_MDIO);
	234	} else {
	235	prop_val.busid = cpu_to_fdt32(
	236	ETH_2_1G_BUS_ID);
	237	prop_val.phyid = cpu_to_fdt32(
	238	ETH_2_1G_PHY_ID);
	239	prop_val.mux_val = cpu_to_fdt32(
	240	ETH_2_1G_MDIO_MUX);
	241	prop_val.phy_mask = cpu_to_fdt32(
	242	ETH_1G_MDIO_PHY_MASK);
	243	prop_val.phy_mode = "rgmii";
	244	pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
	245	ETH_2_MDIO);
	246	}
	247	break;
	248	case SERDES_2_5_G_PROTOCOL:
	249	if (i == 0) {
	250	prop_val.busid = cpu_to_fdt32(
	251	ETH_1_2_5G_BUS_ID);
	252	prop_val.phyid = cpu_to_fdt32(
	253	ETH_1_2_5G_PHY_ID);
	254	prop_val.mux_val = cpu_to_fdt32(
	255	ETH_1_2_5G_MDIO_MUX);
256	prop_val.phy_mask = cpu_to_fdt32(
257	ETH_2_5G_MDIO_PHY_MASK);
258	prop_val.phy_mode = "sgmii-2500";
259	pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
260	ETH_1_MDIO);
261	} else {
262	prop_val.busid = cpu_to_fdt32(
263	ETH_2_2_5G_BUS_ID);
264	prop_val.phyid = cpu_to_fdt32(
265	ETH_2_2_5G_PHY_ID);
266	prop_val.mux_val = cpu_to_fdt32(
267	ETH_2_2_5G_MDIO_MUX);
268	prop_val.phy_mask = cpu_to_fdt32(
269	ETH_2_5G_MDIO_PHY_MASK);
270	prop_val.phy_mode = "sgmii-2500";
271	pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
272	ETH_2_MDIO);
273	}
274	break;
275	default:
276	printf("serdes:[%d]\n", srds_s1);
277	}
278	}
279	}
280
9d044fcb PK	281	#ifdef CONFIG_OF_BOARD_SETUP
	282	int ft_board_setup(void blob, bd_t bd)
	283	{
	284	arch_fixup_fdt(blob);
	285
	286	ft_cpu_setup(blob, bd);
7a8df8ba	287	fdt_fsl_fixup_of_pfe(blob);
9d044fcb PK	288
	289	return 0;
	290	}
	291	#endif