[thirdparty/u-boot.git] / board / freescale / ls1088a / eth_ls1088aqds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017 NXP
 */

#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <hwconfig.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fm_eth.h>
#include <i2c.h>
#include <miiphy.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl-mc/ldpaa_wriop.h>

#include "../common/qixis.h"

#include "ls1088a_qixis.h"

#ifdef CONFIG_FSL_MC_ENET

#define SFP_TX		0

 /* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
 *   Bank 1 -> Lanes A, B, C, D,
 *   Bank 2 -> Lanes A,B, C, D,
 */

 /* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
  * means that the mapping must be determined dynamically, or that the lane
  * maps to something other than a board slot.
  */

static u8 lane_to_slot_fsm1[] = {
	0, 0, 0, 0, 0, 0, 0, 0
};

/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
 * housed.
 */

static int xqsgii_riser_phy_addr[] = {
	XQSGMII_CARD_PHY1_PORT0_ADDR,
	XQSGMII_CARD_PHY2_PORT0_ADDR,
	XQSGMII_CARD_PHY3_PORT0_ADDR,
	XQSGMII_CARD_PHY4_PORT0_ADDR,
	XQSGMII_CARD_PHY3_PORT2_ADDR,
	XQSGMII_CARD_PHY1_PORT2_ADDR,
	XQSGMII_CARD_PHY4_PORT2_ADDR,
	XQSGMII_CARD_PHY2_PORT2_ADDR,
};

static int sgmii_riser_phy_addr[] = {
	SGMII_CARD_PORT1_PHY_ADDR,
	SGMII_CARD_PORT2_PHY_ADDR,
	SGMII_CARD_PORT3_PHY_ADDR,
	SGMII_CARD_PORT4_PHY_ADDR,
};

/* Slot2 does not have EMI connections */
#define EMI_NONE	0xFF
#define EMI1_RGMII1	0
#define EMI1_RGMII2	1
#define EMI1_SLOT1	2

static const char * const mdio_names[] = {
	"LS1088A_QDS_MDIO0",
	"LS1088A_QDS_MDIO1",
	"LS1088A_QDS_MDIO2",
	DEFAULT_WRIOP_MDIO2_NAME,
};

struct ls1088a_qds_mdio {
	u8 muxval;
	struct mii_dev *realbus;
};

static void sgmii_configure_repeater(int dpmac)
{
	struct mii_dev *bus;
	uint8_t a = 0xf;
	int i, j, ret;
	unsigned short value;
	const char *dev = "LS1088A_QDS_MDIO2";
	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
	int i2c_phy_addr = 0;
	int phy_addr = 0;

	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

	/* Set I2c to Slot 1 */
	i2c_write(0x77, 0, 0, &a, 1);

	switch (dpmac) {
	case 1:
		i2c_phy_addr = i2c_addr[1];
		phy_addr = 4;
		break;
	case 2:
		i2c_phy_addr = i2c_addr[0];
		phy_addr = 0;
		break;
	case 3:
		i2c_phy_addr = i2c_addr[3];
		phy_addr = 0xc;
		break;
	case 7:
		i2c_phy_addr = i2c_addr[2];
		phy_addr = 8;
		break;
	}

	/* Check the PHY status */
	ret = miiphy_set_current_dev(dev);
	if (ret > 0)
		goto error;

	bus = mdio_get_current_dev();
	debug("Reading from bus %s\n", bus->name);

	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
	if (ret > 0)
		goto error;

	mdelay(10);
	ret = miiphy_read(dev, phy_addr, 0x11, &value);
	if (ret > 0)
			goto error;

	mdelay(10);

	if ((value & 0xfff) == 0x401) {
		miiphy_write(dev, phy_addr, 0x1f, 0);
		printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
		return;
	}

	for (i = 0; i < 4; i++) {
		for (j = 0; j < 4; j++) {
			a = 0x18;
			i2c_write(i2c_phy_addr, 6, 1, &a, 1);
			a = 0x38;
			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
			a = 0x4;
			i2c_write(i2c_phy_addr, 8, 1, &a, 1);

			i2c_write(i2c_phy_addr, 0xf, 1,
				  &ch_a_eq[i], 1);
			i2c_write(i2c_phy_addr, 0x11, 1,
				  &ch_a_ctl2[j], 1);

			i2c_write(i2c_phy_addr, 0x16, 1,
				  &ch_b_eq[i], 1);
			i2c_write(i2c_phy_addr, 0x18, 1,
				  &ch_b_ctl2[j], 1);

			a = 0x14;
			i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
			a = 0xb5;
			i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
			a = 0x20;
			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
			mdelay(100);
			ret = miiphy_read(dev, phy_addr, 0x11, &value);
			if (ret > 0)
				goto error;

			mdelay(100);
			ret = miiphy_read(dev, phy_addr, 0x11, &value);
			if (ret > 0)
				goto error;

			if ((value & 0xfff) == 0x401) {
				printf("DPMAC %d :PHY is configured ",
				       dpmac);
				printf("after setting repeater 0x%x\n",
				       value);
				i = 5;
				j = 5;
			} else {
				printf("DPMAC %d :PHY is failed to ",
				       dpmac);
				printf("configure the repeater 0x%x\n", value);
			}
		}
	}
	miiphy_write(dev, phy_addr, 0x1f, 0);
error:
	if (ret)
		printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
	return;
}

static void qsgmii_configure_repeater(int dpmac)
{
	uint8_t a = 0xf;
	int i, j;
	int i2c_phy_addr = 0;
	int phy_addr = 0;
	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};

	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

	const char *dev = mdio_names[EMI1_SLOT1];
	int ret = 0;
	unsigned short value;

	/* Set I2c to Slot 1 */
	i2c_write(0x77, 0, 0, &a, 1);

	switch (dpmac) {
	case 7:
	case 8:
	case 9:
	case 10:
		i2c_phy_addr = i2c_addr[2];
		phy_addr = 8;
		break;

	case 3:
	case 4:
	case 5:
	case 6:
		i2c_phy_addr = i2c_addr[3];
		phy_addr = 0xc;
		break;
	}

	/* Check the PHY status */
	ret = miiphy_set_current_dev(dev);
	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
	mdelay(10);
	ret = miiphy_read(dev, phy_addr, 0x11, &value);
	mdelay(10);
	ret = miiphy_read(dev, phy_addr, 0x11, &value);
	mdelay(10);
	if ((value & 0xf) == 0xf) {
		miiphy_write(dev, phy_addr, 0x1f, 0);
		printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
		return;
	}

	for (i = 0; i < 4; i++) {
		for (j = 0; j < 4; j++) {
			a = 0x18;
			i2c_write(i2c_phy_addr, 6, 1, &a, 1);
			a = 0x38;
			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
			a = 0x4;
			i2c_write(i2c_phy_addr, 8, 1, &a, 1);

			i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
			i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);

			i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
			i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);

			a = 0x14;
			i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
			a = 0xb5;
			i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
			a = 0x20;
			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
			mdelay(100);
			ret = miiphy_read(dev, phy_addr, 0x11, &value);
			if (ret > 0)
				goto error;
			mdelay(1);
			ret = miiphy_read(dev, phy_addr, 0x11, &value);
			if (ret > 0)
				goto error;
			mdelay(10);
			if ((value & 0xf) == 0xf) {
				miiphy_write(dev, phy_addr, 0x1f, 0);
				printf("DPMAC %d :PHY is ..... Configured\n",
				       dpmac);
				return;
			}
		}
	}
error:
	printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
	return;
}

static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
{
	return mdio_names[muxval];
}

struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
	struct mii_dev *bus;
	const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);

	if (!name) {
		printf("No bus for muxval %x\n", muxval);
		return NULL;
	}

	bus = miiphy_get_dev_by_name(name);

	if (!bus) {
		printf("No bus by name %s\n", name);
		return NULL;
	}

	return bus;
}

static void ls1088a_qds_enable_SFP_TX(u8 muxval)
{
	u8 brdcfg9;

	brdcfg9 = QIXIS_READ(brdcfg[9]);
	brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
	brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
	QIXIS_WRITE(brdcfg[9], brdcfg9);
}

static void ls1088a_qds_mux_mdio(u8 muxval)
{
	u8 brdcfg4;

	if (muxval <= 5) {
		brdcfg4 = QIXIS_READ(brdcfg[4]);
		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
		QIXIS_WRITE(brdcfg[4], brdcfg4);
	}
}

static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
				 int devad, int regnum)
{
	struct ls1088a_qds_mdio *priv = bus->priv;

	ls1088a_qds_mux_mdio(priv->muxval);

	return priv->realbus->read(priv->realbus, addr, devad, regnum);
}

static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
				  int regnum, u16 value)
{
	struct ls1088a_qds_mdio *priv = bus->priv;

	ls1088a_qds_mux_mdio(priv->muxval);

	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}

static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
{
	struct ls1088a_qds_mdio *priv = bus->priv;

	return priv->realbus->reset(priv->realbus);
}

static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
{
	struct ls1088a_qds_mdio *pmdio;
	struct mii_dev *bus = mdio_alloc();

	if (!bus) {
		printf("Failed to allocate ls1088a_qds MDIO bus\n");
		return -1;
	}

	pmdio = malloc(sizeof(*pmdio));
	if (!pmdio) {
		printf("Failed to allocate ls1088a_qds private data\n");
		free(bus);
		return -1;
	}

	bus->read = ls1088a_qds_mdio_read;
	bus->write = ls1088a_qds_mdio_write;
	bus->reset = ls1088a_qds_mdio_reset;
	sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));

	pmdio->realbus = miiphy_get_dev_by_name(realbusname);

	if (!pmdio->realbus) {
		printf("No bus with name %s\n", realbusname);
		free(bus);
		free(pmdio);
		return -1;
	}

	pmdio->muxval = muxval;
	bus->priv = pmdio;

	return mdio_register(bus);
}

/*
 * Initialize the dpmac_info array.
 *
 */
static void initialize_dpmac_to_slot(void)
{
	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	u32 serdes1_prtcl, cfg;

	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);

	switch (serdes1_prtcl) {
	case 0x12:
		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
		       serdes1_prtcl);
		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
		break;
	case 0x15:
	case 0x1D:
		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
		       serdes1_prtcl);
		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[2] = EMI_NONE;
		lane_to_slot_fsm1[3] = EMI_NONE;
		break;
	case 0x1E:
		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
		       serdes1_prtcl);
		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[3] = EMI_NONE;
		break;
	case 0x3A:
		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
		       serdes1_prtcl);
		lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[1] = EMI_NONE;
		lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
		lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
		break;

	default:
		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
		       __func__, serdes1_prtcl);
		break;
	}
}

void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
{
	struct mii_dev *bus;
	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	u32 serdes1_prtcl, cfg;

	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);

	int *riser_phy_addr;
	char *env_hwconfig = env_get("hwconfig");

	if (hwconfig_f("xqsgmii", env_hwconfig))
		riser_phy_addr = &xqsgii_riser_phy_addr[0];
	else
		riser_phy_addr = &sgmii_riser_phy_addr[0];

	switch (serdes1_prtcl) {
	case 0x12:
	case 0x15:
	case 0x1E:
	case 0x3A:
		switch (dpmac_id) {
		case 1:
			wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
			break;
		case 2:
			wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
			break;
		case 3:
			wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
			break;
		case 7:
			wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
			break;
		default:
			printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
			break;
		}
		break;
	default:
		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
		       __func__, serdes1_prtcl);
		return;
	}
	dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
	bus = mii_dev_for_muxval(EMI1_SLOT1);
	wriop_set_mdio(dpmac_id, bus);
}

void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
{
	struct mii_dev *bus;
	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	u32 serdes1_prtcl, cfg;

	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);

	switch (serdes1_prtcl) {
	case 0x1D:
	case 0x1E:
		switch (dpmac_id) {
		case 3:
		case 4:
		case 5:
		case 6:
			wriop_set_phy_address(dpmac_id, dpmac_id + 9);
			break;
		case 7:
		case 8:
		case 9:
		case 10:
			wriop_set_phy_address(dpmac_id, dpmac_id + 1);
			break;
		}

		dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
		bus = mii_dev_for_muxval(EMI1_SLOT1);
		wriop_set_mdio(dpmac_id, bus);
		break;
	default:
		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
		       serdes1_prtcl);
		break;
	}
}

void ls1088a_handle_phy_interface_xsgmii(int i)
{
	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	u32 serdes1_prtcl, cfg;

	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);

	switch (serdes1_prtcl) {
	case 0x15:
	case 0x1D:
	case 0x1E:
		wriop_set_phy_address(i, i + 26);
		ls1088a_qds_enable_SFP_TX(SFP_TX);
		break;
	default:
		printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
		       serdes1_prtcl);
		break;
	}
}

static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
	u32 serdes1_prtcl, cfg;
	struct mii_dev *bus;

	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
				FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);

	switch (dpmac_id) {
	case 4:
		wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
		dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
		bus = mii_dev_for_muxval(EMI1_RGMII1);
		wriop_set_mdio(dpmac_id, bus);
		break;
	case 5:
		wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
		dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
		bus = mii_dev_for_muxval(EMI1_RGMII2);
		wriop_set_mdio(dpmac_id, bus);
		break;
	default:
		printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
		       serdes1_prtcl);
		break;
	}
}
#endif

int board_eth_init(bd_t *bis)
{
	int error = 0, i;
#ifdef CONFIG_FSL_MC_ENET
	struct memac_mdio_info *memac_mdio0_info;
	char *env_hwconfig = env_get("hwconfig");

	initialize_dpmac_to_slot();

	memac_mdio0_info = (struct memac_mdio_info *)malloc(
					sizeof(struct memac_mdio_info));
	memac_mdio0_info->regs =
		(struct memac_mdio_controller *)
					CONFIG_SYS_FSL_WRIOP1_MDIO1;
	memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;

	/* Register the real MDIO1 bus */
	fm_memac_mdio_init(bis, memac_mdio0_info);
	/* Register the muxing front-ends to the MDIO buses */
	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);

	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
		switch (wriop_get_enet_if(i)) {
		case PHY_INTERFACE_MODE_RGMII:
		case PHY_INTERFACE_MODE_RGMII_ID:
			ls1088a_handle_phy_interface_rgmii(i);
			break;
		case PHY_INTERFACE_MODE_QSGMII:
			ls1088a_handle_phy_interface_qsgmii(i);
			break;
		case PHY_INTERFACE_MODE_SGMII:
			ls1088a_handle_phy_interface_sgmii(i);
			break;
		case PHY_INTERFACE_MODE_XGMII:
			ls1088a_handle_phy_interface_xsgmii(i);
			break;
		default:
			break;

		if (i == 16)
			i = NUM_WRIOP_PORTS;
		}
	}

	error = cpu_eth_init(bis);

	if (hwconfig_f("xqsgmii", env_hwconfig)) {
		for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
			switch (wriop_get_enet_if(i)) {
			case PHY_INTERFACE_MODE_QSGMII:
				qsgmii_configure_repeater(i);
				break;
			case PHY_INTERFACE_MODE_SGMII:
				sgmii_configure_repeater(i);
				break;
			default:
				break;
			}

			if (i == 16)
				i = NUM_WRIOP_PORTS;
		}
	}
#endif
	error = pci_eth_init(bis);
	return error;
}

#if defined(CONFIG_RESET_PHY_R)
void reset_phy(void)
{
	mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7769776a AK	2	/*
7769776a AK	3	* Copyright 2017 NXP
7769776a AK	4	*/
	5
	6	#include <common.h>
	7	#include <netdev.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/fsl_serdes.h>
	10	#include <hwconfig.h>
	11	#include <fsl_mdio.h>
	12	#include <malloc.h>
	13	#include <fm_eth.h>
	14	#include <i2c.h>
	15	#include <miiphy.h>
c48deb90	16	#include <fsl-mc/fsl_mc.h>
7769776a AK	17	#include <fsl-mc/ldpaa_wriop.h>
	18
	19	#include "../common/qixis.h"
	20
	21	#include "ls1088a_qixis.h"
	22
7769776a AK	23	#ifdef CONFIG_FSL_MC_ENET
	24
	25	#define SFP_TX 0
	26
	27	/* - In LS1088A A there are only 16 SERDES lanes, spread across 2 SERDES banks.
	28	* Bank 1 -> Lanes A, B, C, D,
	29	* Bank 2 -> Lanes A,B, C, D,
	30	*/
	31
	32	/* Mapping of 8 SERDES lanes to LS1088A QDS board slots. A value of '0' here
	33	* means that the mapping must be determined dynamically, or that the lane
	34	* maps to something other than a board slot.
	35	*/
	36
	37	static u8 lane_to_slot_fsm1[] = {
	38	0, 0, 0, 0, 0, 0, 0, 0
	39	};
	40
	41	/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
	42	* housed.
	43	*/
	44
	45	static int xqsgii_riser_phy_addr[] = {
	46	XQSGMII_CARD_PHY1_PORT0_ADDR,
	47	XQSGMII_CARD_PHY2_PORT0_ADDR,
	48	XQSGMII_CARD_PHY3_PORT0_ADDR,
	49	XQSGMII_CARD_PHY4_PORT0_ADDR,
	50	XQSGMII_CARD_PHY3_PORT2_ADDR,
	51	XQSGMII_CARD_PHY1_PORT2_ADDR,
	52	XQSGMII_CARD_PHY4_PORT2_ADDR,
	53	XQSGMII_CARD_PHY2_PORT2_ADDR,
	54	};
	55
	56	static int sgmii_riser_phy_addr[] = {
	57	SGMII_CARD_PORT1_PHY_ADDR,
	58	SGMII_CARD_PORT2_PHY_ADDR,
	59	SGMII_CARD_PORT3_PHY_ADDR,
	60	SGMII_CARD_PORT4_PHY_ADDR,
	61	};
	62
	63	/* Slot2 does not have EMI connections */
	64	#define EMI_NONE 0xFF
	65	#define EMI1_RGMII1 0
	66	#define EMI1_RGMII2 1
	67	#define EMI1_SLOT1 2
	68
	69	static const char * const mdio_names[] = {
	70	"LS1088A_QDS_MDIO0",
	71	"LS1088A_QDS_MDIO1",
	72	"LS1088A_QDS_MDIO2",
	73	DEFAULT_WRIOP_MDIO2_NAME,
	74	};
	75
	76	struct ls1088a_qds_mdio {
	77	u8 muxval;
	78	struct mii_dev *realbus;
	79	};
	80
	81	static void sgmii_configure_repeater(int dpmac)
	82	{
	83	struct mii_dev *bus;
	84	uint8_t a = 0xf;
	85	int i, j, ret;
	86	unsigned short value;
87	const char *dev = "LS1088A_QDS_MDIO2";
88	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
89	int i2c_phy_addr = 0;
90	int phy_addr = 0;
91
92	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
93	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
94	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
95	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
96
97	/* Set I2c to Slot 1 */
98	i2c_write(0x77, 0, 0, &a, 1);
99
100	switch (dpmac) {
101	case 1:
102	i2c_phy_addr = i2c_addr[1];
103	phy_addr = 4;
104	break;
105	case 2:
106	i2c_phy_addr = i2c_addr[0];
107	phy_addr = 0;
108	break;
109	case 3:
110	i2c_phy_addr = i2c_addr[3];
111	phy_addr = 0xc;
112	break;
113	case 7:
114	i2c_phy_addr = i2c_addr[2];
115	phy_addr = 8;
116	break;
117	}
118
119	/* Check the PHY status */
120	ret = miiphy_set_current_dev(dev);
121	if (ret > 0)
122	goto error;
123
124	bus = mdio_get_current_dev();
125	debug("Reading from bus %s\n", bus->name);
126
127	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
128	if (ret > 0)
129	goto error;
130
131	mdelay(10);
132	ret = miiphy_read(dev, phy_addr, 0x11, &value);
133	if (ret > 0)
134	goto error;
135
136	mdelay(10);
137
138	if ((value & 0xfff) == 0x401) {
139	miiphy_write(dev, phy_addr, 0x1f, 0);
140	printf("DPMAC %d:PHY is ..... Configured\n", dpmac);
141	return;
142	}
143
144	for (i = 0; i < 4; i++) {
145	for (j = 0; j < 4; j++) {
146	a = 0x18;
147	i2c_write(i2c_phy_addr, 6, 1, &a, 1);
148	a = 0x38;
149	i2c_write(i2c_phy_addr, 4, 1, &a, 1);
150	a = 0x4;
151	i2c_write(i2c_phy_addr, 8, 1, &a, 1);
152
153	i2c_write(i2c_phy_addr, 0xf, 1,
154	&ch_a_eq[i], 1);
155	i2c_write(i2c_phy_addr, 0x11, 1,
156	&ch_a_ctl2[j], 1);
157
158	i2c_write(i2c_phy_addr, 0x16, 1,
159	&ch_b_eq[i], 1);
160	i2c_write(i2c_phy_addr, 0x18, 1,
161	&ch_b_ctl2[j], 1);
162
163	a = 0x14;
164	i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
165	a = 0xb5;
166	i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
167	a = 0x20;
168	i2c_write(i2c_phy_addr, 4, 1, &a, 1);
169	mdelay(100);
170	ret = miiphy_read(dev, phy_addr, 0x11, &value);
171	if (ret > 0)
172	goto error;
173
174	mdelay(100);
175	ret = miiphy_read(dev, phy_addr, 0x11, &value);
176	if (ret > 0)
177	goto error;
178
179	if ((value & 0xfff) == 0x401) {
180	printf("DPMAC %d :PHY is configured ",
181	dpmac);
182	printf("after setting repeater 0x%x\n",
183	value);
184	i = 5;
185	j = 5;
186	} else {
187	printf("DPMAC %d :PHY is failed to ",
188	dpmac);
189	printf("configure the repeater 0x%x\n", value);
190	}
191	}
192	}
193	miiphy_write(dev, phy_addr, 0x1f, 0);
194	error:
195	if (ret)
196	printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac);
197	return;
198	}
199
200	static void qsgmii_configure_repeater(int dpmac)
201	{
202	uint8_t a = 0xf;
203	int i, j;
204	int i2c_phy_addr = 0;
205	int phy_addr = 0;
206	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
207
208	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
209	uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
210	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
211	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
212
213	const char *dev = mdio_names[EMI1_SLOT1];
214	int ret = 0;
215	unsigned short value;
216
217	/* Set I2c to Slot 1 */
218	i2c_write(0x77, 0, 0, &a, 1);
219
220	switch (dpmac) {
221	case 7:
222	case 8:
223	case 9:
224	case 10:
225	i2c_phy_addr = i2c_addr[2];
226	phy_addr = 8;
227	break;
228
229	case 3:
230	case 4:
231	case 5:
232	case 6:
233	i2c_phy_addr = i2c_addr[3];
234	phy_addr = 0xc;
235	break;
236	}
237
238	/* Check the PHY status */
239	ret = miiphy_set_current_dev(dev);
240	ret = miiphy_write(dev, phy_addr, 0x1f, 3);
241	mdelay(10);
242	ret = miiphy_read(dev, phy_addr, 0x11, &value);
243	mdelay(10);
244	ret = miiphy_read(dev, phy_addr, 0x11, &value);
245	mdelay(10);
246	if ((value & 0xf) == 0xf) {
247	miiphy_write(dev, phy_addr, 0x1f, 0);
248	printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
249	return;
250	}
251
252	for (i = 0; i < 4; i++) {
253	for (j = 0; j < 4; j++) {
254	a = 0x18;
255	i2c_write(i2c_phy_addr, 6, 1, &a, 1);
256	a = 0x38;
257	i2c_write(i2c_phy_addr, 4, 1, &a, 1);
258	a = 0x4;
259	i2c_write(i2c_phy_addr, 8, 1, &a, 1);
260
261	i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
262	i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
263
264	i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
265	i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
266
267	a = 0x14;
268	i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
269	a = 0xb5;
270	i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
271	a = 0x20;
272	i2c_write(i2c_phy_addr, 4, 1, &a, 1);
273	mdelay(100);
274	ret = miiphy_read(dev, phy_addr, 0x11, &value);
275	if (ret > 0)
276	goto error;
277	mdelay(1);
278	ret = miiphy_read(dev, phy_addr, 0x11, &value);
279	if (ret > 0)
280	goto error;
281	mdelay(10);
282	if ((value & 0xf) == 0xf) {
283	miiphy_write(dev, phy_addr, 0x1f, 0);
284	printf("DPMAC %d :PHY is ..... Configured\n",
285	dpmac);
286	return;
287	}
288	}
289	}
290	error:
291	printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
292	return;
293	}
294
295	static const char *ls1088a_qds_mdio_name_for_muxval(u8 muxval)
296	{
297	return mdio_names[muxval];
298	}
299
300	struct mii_dev *mii_dev_for_muxval(u8 muxval)
301	{
302	struct mii_dev *bus;
303	const char *name = ls1088a_qds_mdio_name_for_muxval(muxval);
304
305	if (!name) {
306	printf("No bus for muxval %x\n", muxval);
307	return NULL;
308	}
309
310	bus = miiphy_get_dev_by_name(name);
311
312	if (!bus) {
313	printf("No bus by name %s\n", name);
314	return NULL;
315	}
316
317	return bus;
318	}
319
320	static void ls1088a_qds_enable_SFP_TX(u8 muxval)
321	{
322	u8 brdcfg9;
323
324	brdcfg9 = QIXIS_READ(brdcfg[9]);
325	brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
326	brdcfg9 \|= (muxval << BRDCFG9_SFPTX_SHIFT);
327	QIXIS_WRITE(brdcfg[9], brdcfg9);
328	}
329
330	static void ls1088a_qds_mux_mdio(u8 muxval)
331	{
332	u8 brdcfg4;
333
334	if (muxval <= 5) {
335	brdcfg4 = QIXIS_READ(brdcfg[4]);
336	brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
337	brdcfg4 \|= (muxval << BRDCFG4_EMISEL_SHIFT);
338	QIXIS_WRITE(brdcfg[4], brdcfg4);
339	}
340	}
341
342	static int ls1088a_qds_mdio_read(struct mii_dev *bus, int addr,
343	int devad, int regnum)
344	{
345	struct ls1088a_qds_mdio *priv = bus->priv;
346
347	ls1088a_qds_mux_mdio(priv->muxval);
348
349	return priv->realbus->read(priv->realbus, addr, devad, regnum);
350	}
351
352	static int ls1088a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
353	int regnum, u16 value)
354	{
355	struct ls1088a_qds_mdio *priv = bus->priv;
356
357	ls1088a_qds_mux_mdio(priv->muxval);
358
359	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
360	}
361
362	static int ls1088a_qds_mdio_reset(struct mii_dev *bus)
363	{
364	struct ls1088a_qds_mdio *priv = bus->priv;
365
366	return priv->realbus->reset(priv->realbus);
367	}
368
369	static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
370	{
371	struct ls1088a_qds_mdio *pmdio;
372	struct mii_dev *bus = mdio_alloc();
373
374	if (!bus) {
375	printf("Failed to allocate ls1088a_qds MDIO bus\n");
376	return -1;
377	}
378
379	pmdio = malloc(sizeof(*pmdio));
380	if (!pmdio) {
381	printf("Failed to allocate ls1088a_qds private data\n");
382	free(bus);
383	return -1;
384	}
385
386	bus->read = ls1088a_qds_mdio_read;
387	bus->write = ls1088a_qds_mdio_write;
388	bus->reset = ls1088a_qds_mdio_reset;
389	sprintf(bus->name, ls1088a_qds_mdio_name_for_muxval(muxval));
390
391	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
392
393	if (!pmdio->realbus) {
394	printf("No bus with name %s\n", realbusname);
395	free(bus);
396	free(pmdio);
397	return -1;
398	}
399
400	pmdio->muxval = muxval;
401	bus->priv = pmdio;
402
403	return mdio_register(bus);
404	}
405
406	/*
407	* Initialize the dpmac_info array.
408	*
409	*/
410	static void initialize_dpmac_to_slot(void)
411	{
412	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
413	u32 serdes1_prtcl, cfg;
414
415	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
416	FSL_CHASSIS3_SRDS1_PRTCL_MASK;
417	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
418	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
419
420	switch (serdes1_prtcl) {
421	case 0x12:
422	printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
423	serdes1_prtcl);
424	lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
425	lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
426	lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
427	lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
428	break;
429	case 0x15:
430	case 0x1D:
431	printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
432	serdes1_prtcl);
433	lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
434	lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
435	lane_to_slot_fsm1[2] = EMI_NONE;
436	lane_to_slot_fsm1[3] = EMI_NONE;
437	break;
438	case 0x1E:
439	printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
440	serdes1_prtcl);
441	lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
442	lane_to_slot_fsm1[1] = EMI1_SLOT1 - 1;
443	lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
444	lane_to_slot_fsm1[3] = EMI_NONE;
445	break;
446	case 0x3A:
447	printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
448	serdes1_prtcl);
449	lane_to_slot_fsm1[0] = EMI1_SLOT1 - 1;
450	lane_to_slot_fsm1[1] = EMI_NONE;
451	lane_to_slot_fsm1[2] = EMI1_SLOT1 - 1;
452	lane_to_slot_fsm1[3] = EMI1_SLOT1 - 1;
453	break;
454
455	default:
456	printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
457	__func__, serdes1_prtcl);
458	break;
459	}
460	}
461
462	void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
463	{
464	struct mii_dev *bus;
465	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
466	u32 serdes1_prtcl, cfg;
467
468	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
469	FSL_CHASSIS3_SRDS1_PRTCL_MASK;
470	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
471	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
472
473	int *riser_phy_addr;
474	char *env_hwconfig = env_get("hwconfig");
475
476	if (hwconfig_f("xqsgmii", env_hwconfig))
477	riser_phy_addr = &xqsgii_riser_phy_addr[0];
478	else
479	riser_phy_addr = &sgmii_riser_phy_addr[0];
480
481	switch (serdes1_prtcl) {
482	case 0x12:
483	case 0x15:
484	case 0x1E:
485	case 0x3A:
486	switch (dpmac_id) {
487	case 1:
488	wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
489	break;
490	case 2:
491	wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
492	break;
493	case 3:
494	wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
495	break;
496	case 7:
497	wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
498	break;
499	default:
500	printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
501	break;
502	}
503	break;
504	default:
505	printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
506	__func__, serdes1_prtcl);
507	return;
508	}
509	dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
510	bus = mii_dev_for_muxval(EMI1_SLOT1);
511	wriop_set_mdio(dpmac_id, bus);
512	}
513
514	void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
515	{
516	struct mii_dev *bus;
517	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
518	u32 serdes1_prtcl, cfg;
519
520	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
521	FSL_CHASSIS3_SRDS1_PRTCL_MASK;
522	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
523	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
524
525	switch (serdes1_prtcl) {
526	case 0x1D:
527	case 0x1E:
528	switch (dpmac_id) {
529	case 3:
530	case 4:
531	case 5:
532	case 6:
533	wriop_set_phy_address(dpmac_id, dpmac_id + 9);
534	break;
535	case 7:
536	case 8:
537	case 9:
538	case 10:
539	wriop_set_phy_address(dpmac_id, dpmac_id + 1);
540	break;
541	}
542
543	dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
544	bus = mii_dev_for_muxval(EMI1_SLOT1);
545	wriop_set_mdio(dpmac_id, bus);
546	break;
547	default:
548	printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
549	serdes1_prtcl);
550	break;
551	}
552	}
553
554	void ls1088a_handle_phy_interface_xsgmii(int i)
555	{
556	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
557	u32 serdes1_prtcl, cfg;
558
559	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
560	FSL_CHASSIS3_SRDS1_PRTCL_MASK;
561	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
562	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
563
564	switch (serdes1_prtcl) {
565	case 0x15:
566	case 0x1D:
567	case 0x1E:
568	wriop_set_phy_address(i, i + 26);
569	ls1088a_qds_enable_SFP_TX(SFP_TX);
570	break;
571	default:
572	printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
573	serdes1_prtcl);
574	break;
575	}
576	}
9f244b35 PK	577
	578	static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
	579	{
	580	struct ccsr_gur __iomem gur = (void )CONFIG_SYS_FSL_GUTS_ADDR;
	581	u32 serdes1_prtcl, cfg;
	582	struct mii_dev *bus;
	583
	584	cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
	585	FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	586	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
	587	serdes1_prtcl = serdes_get_number(FSL_SRDS_1, cfg);
	588
	589	switch (dpmac_id) {
	590	case 4:
	591	wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
	592	dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
	593	bus = mii_dev_for_muxval(EMI1_RGMII1);
	594	wriop_set_mdio(dpmac_id, bus);
	595	break;
	596	case 5:
	597	wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
	598	dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
	599	bus = mii_dev_for_muxval(EMI1_RGMII2);
	600	wriop_set_mdio(dpmac_id, bus);
	601	break;
	602	default:
	603	printf("qds: WRIOP: Unsupported RGMII SerDes Protocol 0x%02x\n",
	604	serdes1_prtcl);
	605	break;
	606	}
	607	}
7769776a AK	608	#endif
	609
	610	int board_eth_init(bd_t *bis)
	611	{
	612	int error = 0, i;
7769776a AK	613	#ifdef CONFIG_FSL_MC_ENET
	614	struct memac_mdio_info *memac_mdio0_info;
	615	char *env_hwconfig = env_get("hwconfig");
	616
	617	initialize_dpmac_to_slot();
	618
	619	memac_mdio0_info = (struct memac_mdio_info *)malloc(
	620	sizeof(struct memac_mdio_info));
	621	memac_mdio0_info->regs =
	622	(struct memac_mdio_controller *)
	623	CONFIG_SYS_FSL_WRIOP1_MDIO1;
	624	memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
	625
	626	/* Register the real MDIO1 bus */
	627	fm_memac_mdio_init(bis, memac_mdio0_info);
7769776a AK	628	/* Register the muxing front-ends to the MDIO buses */
	629	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
	630	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
	631	ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
	632
	633	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
	634	switch (wriop_get_enet_if(i)) {
9f244b35	635	case PHY_INTERFACE_MODE_RGMII:
2af1b08a	636	case PHY_INTERFACE_MODE_RGMII_ID:
9f244b35 PK	637	ls1088a_handle_phy_interface_rgmii(i);
9f244b35 PK	638	break;
7769776a AK	639	case PHY_INTERFACE_MODE_QSGMII:
	640	ls1088a_handle_phy_interface_qsgmii(i);
	641	break;
	642	case PHY_INTERFACE_MODE_SGMII:
	643	ls1088a_handle_phy_interface_sgmii(i);
	644	break;
	645	case PHY_INTERFACE_MODE_XGMII:
	646	ls1088a_handle_phy_interface_xsgmii(i);
	647	break;
	648	default:
	649	break;
	650
	651	if (i == 16)
	652	i = NUM_WRIOP_PORTS;
	653	}
	654	}
	655
7769776a AK	656	error = cpu_eth_init(bis);
	657
	658	if (hwconfig_f("xqsgmii", env_hwconfig)) {
	659	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
	660	switch (wriop_get_enet_if(i)) {
	661	case PHY_INTERFACE_MODE_QSGMII:
	662	qsgmii_configure_repeater(i);
	663	break;
	664	case PHY_INTERFACE_MODE_SGMII:
	665	sgmii_configure_repeater(i);
	666	break;
	667	default:
	668	break;
	669	}
	670
	671	if (i == 16)
	672	i = NUM_WRIOP_PORTS;
	673	}
	674	}
	675	#endif
	676	error = pci_eth_init(bis);
	677	return error;
	678	}
c48deb90 BP	679
	680	#if defined(CONFIG_RESET_PHY_R)
	681	void reset_phy(void)
	682	{
	683	mc_env_boot();
	684	}
	685	#endif /* CONFIG_RESET_PHY_R */