[people/ms/u-boot.git] / board / freescale / ls2080aqds / ls2080aqds.c

/*
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>

#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)

DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
	char buf[64];
	u8 sw;
	static const char *const freq[] = {"100", "125", "156.25",
					    "100 separate SSCG"};
	int clock;

	cpu_name(buf);
	printf("Board: %s-QDS, ", buf);

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);

	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x8)
		puts("PromJet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else if (sw == 0x15)
		printf("IFCCard\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d (%s), build %d",
	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
	       (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));

	/*
	 * Display the actual SERDES reference clocks as configured by the
	 * dip switches on the board.  Note that the SWx registers could
	 * technically be set to force the reference clocks to match the
	 * values that the SERDES expects (or vice versa).  For now, however,
	 * we just display both values and hope the user notices when they
	 * don't match.
	 */
	puts("SERDES1 Reference : ");
	sw = QIXIS_READ(brdcfg[2]);
	clock = (sw >> 6) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 4) & 3;
	printf("Clock2 = %sMHz", freq[clock]);

	puts("\nSERDES2 Reference : ");
	clock = (sw >> 2) & 3;
	printf("Clock1 = %sMHz ", freq[clock]);
	clock = (sw >> 0) & 3;
	printf("Clock2 = %sMHz\n", freq[clock]);

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);

	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}
	return 66666666;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int config_board_mux(int ctrl_type)
{
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);

	return 0;
}

int board_init(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;

	init_final_memctl_regs();

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = getenv("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	rtc_enable_32khz_output();

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch3_early_init_f();
	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

int dram_init(void)
{
	gd->ram_size = initdram(0);

	return 0;
}

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_DEBUG_SERVER
	debug_server_init();
#endif

	return 0;
}
#endif

unsigned long get_dram_size_to_hide(void)
{
	unsigned long dram_to_hide = 0;

/* Carve the Debug Server private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_DEBUG_SERVER
	dram_to_hide += debug_server_get_dram_block_size();
#endif

/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET
	dram_to_hide += mc_get_dram_block_size();
#endif

	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
}

#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl,dprc@0");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0)
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	int err;
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

	fdt_fixup_memory_banks(blob, base, size, 2);

#ifdef CONFIG_FSL_MC_ENET
	fdt_fixup_board_enet(blob);
	err = fsl_mc_ldpaa_exit(bd);
	if (err)
		return err;
#endif

	return 0;
}
#endif

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}
Commit	Line	Data
7288c2c2 YS	1	/*
	2	* Copyright 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
	7	#include <malloc.h>
	8	#include <errno.h>
	9	#include <netdev.h>
	10	#include <fsl_ifc.h>
	11	#include <fsl_ddr.h>
	12	#include <asm/io.h>
	13	#include <fdt_support.h>
	14	#include <libfdt.h>
	15	#include <fsl_debug_server.h>
	16	#include <fsl-mc/fsl_mc.h>
	17	#include <environment.h>
	18	#include <i2c.h>
7fb79e65	19	#include <rtc.h>
9f3183d2	20	#include <asm/arch/soc.h>
e71a980a	21	#include <hwconfig.h>
7288c2c2 YS	22
7288c2c2 YS	23	#include "../common/qixis.h"
44937214	24	#include "ls2080aqds_qixis.h"
7288c2c2	25
e71a980a HW	26	#define PIN_MUX_SEL_SDHC 0x00
	27	#define PIN_MUX_SEL_DSPI 0x0a
	28
	29	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
	30
7288c2c2 YS	31	DECLARE_GLOBAL_DATA_PTR;
7288c2c2 YS	32
e71a980a HW	33	enum {
	34	MUX_TYPE_SDHC,
	35	MUX_TYPE_DSPI,
	36	};
	37
7288c2c2 YS	38	unsigned long long get_qixis_addr(void)
	39	{
	40	unsigned long long addr;
	41
	42	if (gd->flags & GD_FLG_RELOC)
	43	addr = QIXIS_BASE_PHYS;
	44	else
	45	addr = QIXIS_BASE_PHYS_EARLY;
	46
	47	/*
	48	* IFC address under 256MB is mapped to 0x30000000, any address above
	49	* is mapped to 0x5_10000000 up to 4GB.
	50	*/
	51	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	52
	53	return addr;
	54	}
	55
	56	int checkboard(void)
	57	{
	58	char buf[64];
	59	u8 sw;
	60	static const char *const freq[] = {"100", "125", "156.25",
	61	"100 separate SSCG"};
	62	int clock;
	63
ff1b8e3f PK	64	cpu_name(buf);
	65	printf("Board: %s-QDS, ", buf);
	66
7288c2c2	67	sw = QIXIS_READ(arch);
7288c2c2 YS	68	printf("Board Arch: V%d, ", sw >> 4);
	69	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	70
ff1b8e3f PK	71	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
ff1b8e3f PK	72
7288c2c2 YS	73	sw = QIXIS_READ(brdcfg[0]);
	74	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	75
	76	if (sw < 0x8)
	77	printf("vBank: %d\n", sw);
	78	else if (sw == 0x8)
	79	puts("PromJet\n");
	80	else if (sw == 0x9)
	81	puts("NAND\n");
	82	else if (sw == 0x15)
	83	printf("IFCCard\n");
	84	else
	85	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	86
	87	printf("FPGA: v%d (%s), build %d",
	88	(int)QIXIS_READ(scver), qixis_read_tag(buf),
	89	(int)qixis_read_minor());
	90	/* the timestamp string contains "\n" at the end */
	91	printf(" on %s", qixis_read_time(buf));
	92
	93	/*
	94	* Display the actual SERDES reference clocks as configured by the
	95	* dip switches on the board. Note that the SWx registers could
	96	* technically be set to force the reference clocks to match the
	97	* values that the SERDES expects (or vice versa). For now, however,
	98	* we just display both values and hope the user notices when they
	99	* don't match.
	100	*/
	101	puts("SERDES1 Reference : ");
	102	sw = QIXIS_READ(brdcfg[2]);
	103	clock = (sw >> 6) & 3;
	104	printf("Clock1 = %sMHz ", freq[clock]);
	105	clock = (sw >> 4) & 3;
	106	printf("Clock2 = %sMHz", freq[clock]);
	107
	108	puts("\nSERDES2 Reference : ");
	109	clock = (sw >> 2) & 3;
	110	printf("Clock1 = %sMHz ", freq[clock]);
	111	clock = (sw >> 0) & 3;
	112	printf("Clock2 = %sMHz\n", freq[clock]);
	113
	114	return 0;
	115	}
	116
	117	unsigned long get_board_sys_clk(void)
	118	{
	119	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	120
	121	switch (sysclk_conf & 0x0F) {
	122	case QIXIS_SYSCLK_83:
	123	return 83333333;
	124	case QIXIS_SYSCLK_100:
	125	return 100000000;
	126	case QIXIS_SYSCLK_125:
	127	return 125000000;
	128	case QIXIS_SYSCLK_133:
	129	return 133333333;
	130	case QIXIS_SYSCLK_150:
	131	return 150000000;
	132	case QIXIS_SYSCLK_160:
	133	return 160000000;
	134	case QIXIS_SYSCLK_166:
	135	return 166666666;
	136	}
137	return 66666666;
138	}
139
140	unsigned long get_board_ddr_clk(void)
141	{
142	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
143
144	switch ((ddrclk_conf & 0x30) >> 4) {
145	case QIXIS_DDRCLK_100:
146	return 100000000;
147	case QIXIS_DDRCLK_125:
148	return 125000000;
149	case QIXIS_DDRCLK_133:
150	return 133333333;
151	}
152	return 66666666;
153	}
154
155	int select_i2c_ch_pca9547(u8 ch)
156	{
157	int ret;
158
159	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
160	if (ret) {
161	puts("PCA: failed to select proper channel\n");
162	return ret;
163	}
164
165	return 0;
166	}
167
e71a980a HW	168	int config_board_mux(int ctrl_type)
	169	{
	170	u8 reg5;
	171
	172	reg5 = QIXIS_READ(brdcfg[5]);
	173
	174	switch (ctrl_type) {
	175	case MUX_TYPE_SDHC:
	176	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	177	break;
	178	case MUX_TYPE_DSPI:
	179	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	180	break;
	181	default:
	182	printf("Wrong mux interface type\n");
	183	return -1;
	184	}
	185
	186	QIXIS_WRITE(brdcfg[5], reg5);
	187
	188	return 0;
	189	}
	190
7288c2c2 YS	191	int board_init(void)
7288c2c2 YS	192	{
e71a980a HW	193	char *env_hwconfig;
	194	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	195	u32 val;
	196
7288c2c2 YS	197	init_final_memctl_regs();
7288c2c2 YS	198
e71a980a HW	199	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
	200
	201	env_hwconfig = getenv("hwconfig");
	202
	203	if (hwconfig_f("dspi", env_hwconfig) &&
	204	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	205	config_board_mux(MUX_TYPE_DSPI);
	206	else
	207	config_board_mux(MUX_TYPE_SDHC);
	208
7288c2c2 YS	209	#ifdef CONFIG_ENV_IS_NOWHERE
	210	gd->env_addr = (ulong)&default_environment[0];
	211	#endif
	212	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
7fb79e65	213	rtc_enable_32khz_output();
7288c2c2 YS	214
	215	return 0;
	216	}
	217
	218	int board_early_init_f(void)
	219	{
	220	fsl_lsch3_early_init_f();
	221	return 0;
	222	}
	223
	224	void detail_board_ddr_info(void)
	225	{
	226	puts("\nDDR ");
	227	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	228	print_ddr_info(0);
44937214	229	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
7288c2c2 YS	230	if (gd->bd->bi_dram[2].size) {
	231	puts("\nDP-DDR ");
	232	print_size(gd->bd->bi_dram[2].size, "");
	233	print_ddr_info(CONFIG_DP_DDR_CTRL);
	234	}
44937214	235	#endif
7288c2c2 YS	236	}
	237
	238	int dram_init(void)
	239	{
	240	gd->ram_size = initdram(0);
	241
	242	return 0;
	243	}
	244
	245	#if defined(CONFIG_ARCH_MISC_INIT)
	246	int arch_misc_init(void)
	247	{
	248	#ifdef CONFIG_FSL_DEBUG_SERVER
	249	debug_server_init();
	250	#endif
	251
	252	return 0;
	253	}
	254	#endif
	255
	256	unsigned long get_dram_size_to_hide(void)
	257	{
	258	unsigned long dram_to_hide = 0;
	259
	260	/* Carve the Debug Server private DRAM block from the end of DRAM */
	261	#ifdef CONFIG_FSL_DEBUG_SERVER
	262	dram_to_hide += debug_server_get_dram_block_size();
	263	#endif
	264
	265	/* Carve the MC private DRAM block from the end of DRAM */
	266	#ifdef CONFIG_FSL_MC_ENET
	267	dram_to_hide += mc_get_dram_block_size();
	268	#endif
	269
5c055089	270	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
7288c2c2 YS	271	}
7288c2c2 YS	272
7288c2c2 YS	273	#ifdef CONFIG_FSL_MC_ENET
	274	void fdt_fixup_board_enet(void *fdt)
	275	{
	276	int offset;
	277
	278	offset = fdt_path_offset(fdt, "/fsl-mc");
	279
	280	if (offset < 0)
	281	offset = fdt_path_offset(fdt, "/fsl,dprc@0");
	282
	283	if (offset < 0) {
	284	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	285	__func__, offset);
	286	return;
	287	}
	288
	289	if (get_mc_boot_status() == 0)
	290	fdt_status_okay(fdt, offset);
	291	else
	292	fdt_status_fail(fdt, offset);
	293	}
	294	#endif
	295
	296	#ifdef CONFIG_OF_BOARD_SETUP
	297	int ft_board_setup(void blob, bd_t bd)
	298	{
1730a17d	299	int err;
a2dc818f BS	300	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	301	u64 size[CONFIG_NR_DRAM_BANKS];
7288c2c2 YS	302
	303	ft_cpu_setup(blob, bd);
	304
a2dc818f BS	305	/* fixup DT for the two GPP DDR banks */
	306	base[0] = gd->bd->bi_dram[0].start;
	307	size[0] = gd->bd->bi_dram[0].size;
	308	base[1] = gd->bd->bi_dram[1].start;
	309	size[1] = gd->bd->bi_dram[1].size;
	310
	311	fdt_fixup_memory_banks(blob, base, size, 2);
7288c2c2 YS	312
	313	#ifdef CONFIG_FSL_MC_ENET
	314	fdt_fixup_board_enet(blob);
1730a17d PK	315	err = fsl_mc_ldpaa_exit(bd);
	316	if (err)
	317	return err;
7288c2c2 YS	318	#endif
	319
	320	return 0;
	321	}
	322	#endif
	323
	324	void qixis_dump_switch(void)
	325	{
	326	int i, nr_of_cfgsw;
	327
	328	QIXIS_WRITE(cms[0], 0x00);
	329	nr_of_cfgsw = QIXIS_READ(cms[1]);
	330
	331	puts("DIP switch settings dump:\n");
	332	for (i = 1; i <= nr_of_cfgsw; i++) {
	333	QIXIS_WRITE(cms[0], i);
	334	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	335	}
	336	}