[people/ms/u-boot.git] / board / freescale / ls2085ardb / ls2085ardb.c

/*
 * Copyright 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
#include <libfdt.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
#include <environment.h>
#include <i2c.h>
#include <asm/arch/soc.h>

#include "../common/qixis.h"
#include "ls2085ardb_qixis.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
	u8 sw;
	char buf[15];

	cpu_name(buf);
	printf("Board: %s-RDB, ", buf);

	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x9)
		puts("NAND\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));

	puts("SERDES1 Reference : ");
	printf("Clock1 = 156.25MHz ");
	printf("Clock2 = 156.25MHz");

	puts("\nSERDES2 Reference : ");
	printf("Clock1 = 100MHz ");
	printf("Clock2 = 100MHz\n");

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int config_board_mux(int ctrl_type)
{
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);

	return 0;
}

int board_init(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;

	init_final_memctl_regs();

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = getenv("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch3_early_init_f();
	return 0;
}

int misc_init_r(void)
{
	if (hwconfig("sdhc"))
		config_board_mux(MUX_TYPE_SDHC);

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
	if (gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
}

int dram_init(void)
{
	gd->ram_size = initdram(0);

	return 0;
}

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_DEBUG_SERVER
	debug_server_init();
#endif

	return 0;
}
#endif

unsigned long get_dram_size_to_hide(void)
{
	unsigned long dram_to_hide = 0;

/* Carve the Debug Server private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_DEBUG_SERVER
	dram_to_hide += debug_server_get_dram_block_size();
#endif

/* Carve the MC private DRAM block from the end of DRAM */
#ifdef CONFIG_FSL_MC_ENET
	dram_to_hide += mc_get_dram_block_size();
#endif

	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
}

#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl,dprc@0");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0)
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	int err;
	u64 base[CONFIG_NR_DRAM_BANKS];
	u64 size[CONFIG_NR_DRAM_BANKS];

	ft_cpu_setup(blob, bd);

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

	fdt_fixup_memory_banks(blob, base, size, 2);

#ifdef CONFIG_FSL_MC_ENET
	fdt_fixup_board_enet(blob);
	err = fsl_mc_ldpaa_exit(bd);
	if (err)
		return err;
#endif

	return 0;
}
#endif

void qixis_dump_switch(void)
{
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
}

/*
 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 * Both slots has 0x54, resulting 2nd slot unusable.
 */
void update_spd_address(unsigned int ctrl_num,
			unsigned int slot,
			unsigned int *addr)
{
	u8 sw;

	sw = QIXIS_READ(arch);
	if ((sw & 0xf) < 0x3) {
		if (ctrl_num == 1 && slot == 0)
			*addr = SPD_EEPROM_ADDRESS4;
		else if (ctrl_num == 1 && slot == 1)
			*addr = SPD_EEPROM_ADDRESS3;
	}
}
Commit	Line	Data
e2b65ea9 YS	1	/*
	2	* Copyright 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#include <common.h>
	7	#include <malloc.h>
	8	#include <errno.h>
	9	#include <netdev.h>
	10	#include <fsl_ifc.h>
	11	#include <fsl_ddr.h>
	12	#include <asm/io.h>
5a4d744c	13	#include <hwconfig.h>
e2b65ea9 YS	14	#include <fdt_support.h>
	15	#include <libfdt.h>
	16	#include <fsl_debug_server.h>
	17	#include <fsl-mc/fsl_mc.h>
	18	#include <environment.h>
	19	#include <i2c.h>
9f3183d2	20	#include <asm/arch/soc.h>
e2b65ea9 YS	21
	22	#include "../common/qixis.h"
	23	#include "ls2085ardb_qixis.h"
	24
5a4d744c	25	#define PIN_MUX_SEL_SDHC 0x00
5989df7e	26	#define PIN_MUX_SEL_DSPI 0x0a
5a4d744c YL	27
5a4d744c YL	28	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
e2b65ea9 YS	29	DECLARE_GLOBAL_DATA_PTR;
e2b65ea9 YS	30
5a4d744c YL	31	enum {
5a4d744c YL	32	MUX_TYPE_SDHC,
5989df7e	33	MUX_TYPE_DSPI,
5a4d744c YL	34	};
5a4d744c YL	35
e2b65ea9 YS	36	unsigned long long get_qixis_addr(void)
	37	{
	38	unsigned long long addr;
	39
	40	if (gd->flags & GD_FLG_RELOC)
	41	addr = QIXIS_BASE_PHYS;
	42	else
	43	addr = QIXIS_BASE_PHYS_EARLY;
	44
	45	/*
	46	* IFC address under 256MB is mapped to 0x30000000, any address above
	47	* is mapped to 0x5_10000000 up to 4GB.
	48	*/
	49	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	50
	51	return addr;
	52	}
	53
	54	int checkboard(void)
	55	{
	56	u8 sw;
ff1b8e3f PK	57	char buf[15];
	58
	59	cpu_name(buf);
	60	printf("Board: %s-RDB, ", buf);
e2b65ea9 YS	61
e2b65ea9 YS	62	sw = QIXIS_READ(arch);
e2b65ea9	63	printf("Board Arch: V%d, ", sw >> 4);
27df54b1	64	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
e2b65ea9 YS	65
	66	sw = QIXIS_READ(brdcfg[0]);
	67	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	68
	69	if (sw < 0x8)
	70	printf("vBank: %d\n", sw);
	71	else if (sw == 0x9)
	72	puts("NAND\n");
	73	else
	74	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	75
	76	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
	77
	78	puts("SERDES1 Reference : ");
	79	printf("Clock1 = 156.25MHz ");
	80	printf("Clock2 = 156.25MHz");
	81
	82	puts("\nSERDES2 Reference : ");
	83	printf("Clock1 = 100MHz ");
	84	printf("Clock2 = 100MHz\n");
	85
	86	return 0;
	87	}
	88
	89	unsigned long get_board_sys_clk(void)
	90	{
	91	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	92
	93	switch (sysclk_conf & 0x0F) {
	94	case QIXIS_SYSCLK_83:
	95	return 83333333;
	96	case QIXIS_SYSCLK_100:
	97	return 100000000;
	98	case QIXIS_SYSCLK_125:
	99	return 125000000;
	100	case QIXIS_SYSCLK_133:
	101	return 133333333;
	102	case QIXIS_SYSCLK_150:
	103	return 150000000;
	104	case QIXIS_SYSCLK_160:
	105	return 160000000;
	106	case QIXIS_SYSCLK_166:
	107	return 166666666;
	108	}
	109	return 66666666;
	110	}
	111
	112	int select_i2c_ch_pca9547(u8 ch)
	113	{
	114	int ret;
	115
	116	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	117	if (ret) {
	118	puts("PCA: failed to select proper channel\n");
	119	return ret;
	120	}
	121
	122	return 0;
	123	}
	124
5a4d744c YL	125	int config_board_mux(int ctrl_type)
	126	{
	127	u8 reg5;
	128
	129	reg5 = QIXIS_READ(brdcfg[5]);
	130
	131	switch (ctrl_type) {
	132	case MUX_TYPE_SDHC:
	133	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	134	break;
5989df7e HW	135	case MUX_TYPE_DSPI:
	136	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	137	break;
5a4d744c YL	138	default:
	139	printf("Wrong mux interface type\n");
	140	return -1;
	141	}
	142
	143	QIXIS_WRITE(brdcfg[5], reg5);
	144
	145	return 0;
	146	}
	147
5989df7e HW	148	int board_init(void)
	149	{
	150	char *env_hwconfig;
	151	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	152	u32 val;
	153
	154	init_final_memctl_regs();
	155
	156	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
	157
	158	env_hwconfig = getenv("hwconfig");
	159
	160	if (hwconfig_f("dspi", env_hwconfig) &&
	161	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	162	config_board_mux(MUX_TYPE_DSPI);
	163	else
	164	config_board_mux(MUX_TYPE_SDHC);
	165
	166	#ifdef CONFIG_ENV_IS_NOWHERE
	167	gd->env_addr = (ulong)&default_environment[0];
	168	#endif
	169	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	170
	171	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
	172
	173	return 0;
	174	}
	175
	176	int board_early_init_f(void)
	177	{
	178	fsl_lsch3_early_init_f();
	179	return 0;
	180	}
	181
5a4d744c YL	182	int misc_init_r(void)
	183	{
	184	if (hwconfig("sdhc"))
	185	config_board_mux(MUX_TYPE_SDHC);
	186
	187	return 0;
	188	}
	189
e2b65ea9 YS	190	void detail_board_ddr_info(void)
	191	{
	192	puts("\nDDR ");
	193	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	194	print_ddr_info(0);
	195	if (gd->bd->bi_dram[2].size) {
	196	puts("\nDP-DDR ");
	197	print_size(gd->bd->bi_dram[2].size, "");
	198	print_ddr_info(CONFIG_DP_DDR_CTRL);
	199	}
	200	}
	201
	202	int dram_init(void)
	203	{
	204	gd->ram_size = initdram(0);
	205
	206	return 0;
	207	}
	208
	209	#if defined(CONFIG_ARCH_MISC_INIT)
	210	int arch_misc_init(void)
	211	{
	212	#ifdef CONFIG_FSL_DEBUG_SERVER
	213	debug_server_init();
	214	#endif
	215
	216	return 0;
	217	}
	218	#endif
	219
	220	unsigned long get_dram_size_to_hide(void)
	221	{
	222	unsigned long dram_to_hide = 0;
	223
	224	/* Carve the Debug Server private DRAM block from the end of DRAM */
	225	#ifdef CONFIG_FSL_DEBUG_SERVER
	226	dram_to_hide += debug_server_get_dram_block_size();
	227	#endif
	228
	229	/* Carve the MC private DRAM block from the end of DRAM */
	230	#ifdef CONFIG_FSL_MC_ENET
	231	dram_to_hide += mc_get_dram_block_size();
	232	#endif
	233
5c055089	234	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
e2b65ea9 YS	235	}
e2b65ea9 YS	236
e2b65ea9 YS	237	#ifdef CONFIG_FSL_MC_ENET
	238	void fdt_fixup_board_enet(void *fdt)
	239	{
	240	int offset;
	241
	242	offset = fdt_path_offset(fdt, "/fsl-mc");
	243
	244	if (offset < 0)
	245	offset = fdt_path_offset(fdt, "/fsl,dprc@0");
	246
	247	if (offset < 0) {
	248	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	249	__func__, offset);
	250	return;
	251	}
	252
	253	if (get_mc_boot_status() == 0)
	254	fdt_status_okay(fdt, offset);
	255	else
	256	fdt_status_fail(fdt, offset);
	257	}
	258	#endif
	259
	260	#ifdef CONFIG_OF_BOARD_SETUP
	261	int ft_board_setup(void blob, bd_t bd)
	262	{
1730a17d	263	int err;
a2dc818f BS	264	u64 base[CONFIG_NR_DRAM_BANKS];
a2dc818f BS	265	u64 size[CONFIG_NR_DRAM_BANKS];
e2b65ea9 YS	266
	267	ft_cpu_setup(blob, bd);
	268
a2dc818f BS	269	/* fixup DT for the two GPP DDR banks */
	270	base[0] = gd->bd->bi_dram[0].start;
	271	size[0] = gd->bd->bi_dram[0].size;
	272	base[1] = gd->bd->bi_dram[1].start;
	273	size[1] = gd->bd->bi_dram[1].size;
	274
	275	fdt_fixup_memory_banks(blob, base, size, 2);
e2b65ea9 YS	276
	277	#ifdef CONFIG_FSL_MC_ENET
	278	fdt_fixup_board_enet(blob);
1730a17d PK	279	err = fsl_mc_ldpaa_exit(bd);
	280	if (err)
	281	return err;
e2b65ea9 YS	282	#endif
	283
	284	return 0;
	285	}
	286	#endif
	287
	288	void qixis_dump_switch(void)
	289	{
	290	int i, nr_of_cfgsw;
	291
	292	QIXIS_WRITE(cms[0], 0x00);
	293	nr_of_cfgsw = QIXIS_READ(cms[1]);
	294
	295	puts("DIP switch settings dump:\n");
	296	for (i = 1; i <= nr_of_cfgsw; i++) {
	297	QIXIS_WRITE(cms[0], i);
	298	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	299	}
	300	}
fc7b3855 YS	301
	302	/*
	303	* Board rev C and earlier has duplicated I2C addresses for 2nd controller.
	304	* Both slots has 0x54, resulting 2nd slot unusable.
	305	*/
	306	void update_spd_address(unsigned int ctrl_num,
	307	unsigned int slot,
	308	unsigned int *addr)
	309	{
	310	u8 sw;
	311
	312	sw = QIXIS_READ(arch);
	313	if ((sw & 0xf) < 0x3) {
	314	if (ctrl_num == 1 && slot == 0)
	315	*addr = SPD_EEPROM_ADDRESS4;
	316	else if (ctrl_num == 1 && slot == 1)
	317	*addr = SPD_EEPROM_ADDRESS3;
	318	}
	319	}