[thirdparty/u-boot.git] / board / freescale / m5253demo / m5253demo.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 */

#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/immap.h>
#include <netdev.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	puts("Board: ");
	puts("Freescale MCF5253 DEMO\n");
	return 0;
};

int dram_init(void)
{
	u32 dramsize = 0;

	/*
	 * Check to see if the SDRAM has already been initialized
	 * by a run control tool
	 */
	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
		u32 RC, temp;

		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
		RC = (RC * 15) >> 4;

		/* Initialize DRAM Control Register: DCR */
		mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
		__asm__("nop");

		mbar_writeLong(MCFSIM_DACR0, 0x00003224);
		__asm__("nop");

		/* Initialize DMR0 */
		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
		temp = (dramsize - 1) & 0xFFFC0000;
		mbar_writeLong(MCFSIM_DMR0, temp | 1);
		__asm__("nop");

		mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
		mb();
		__asm__("nop");

		/* Write to this block to initiate precharge */
		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
		mb();
		__asm__("nop");

		/* Set RE bit in DACR */
		mbar_writeLong(MCFSIM_DACR0,
			       mbar_readLong(MCFSIM_DACR0) | 0x8000);
		__asm__("nop");

		/* Wait for at least 8 auto refresh cycles to occur */
		udelay(500);

		/* Finish the configuration by issuing the MRS */
		mbar_writeLong(MCFSIM_DACR0,
			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
		__asm__("nop");

		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
		mb();
	}

	gd->ram_size = dramsize;

	return 0;
}

int testdram(void)
{
	/* TODO: XXX XXX XXX */
	printf("DRAM test not implemented!\n");

	return (0);
}

#ifdef CONFIG_IDE
#include <ata.h>
int ide_preinit(void)
{
	return (0);
}

void ide_set_reset(int idereset)
{
	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
	long period;
	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
	{50, 125, 45, 20, 35, 5, 15, 0, 35},	/* PIO 1 */
	{30, 100, 30, 15, 20, 5, 10, 0, 35},	/* PIO 2 */
	{30, 80, 30, 10, 20, 5, 10, 0, 35},	/* PIO 3 */
	{25, 70, 20, 10, 20, 5, 10, 0, 35}	/* PIO 4 */
	};

	if (idereset) {
		/* control reset */
		out_8(&ata->cr, 0);
		udelay(100);
	} else {
		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);

#define CALC_TIMING(t) (t + period - 1) / period
		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */

		/*ata->ton = CALC_TIMING (180); */
		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));

		/* IORDY enable */
		out_8(&ata->cr, 0x40);
		udelay(2000);
		/* IORDY enable */
		setbits_8(&ata->cr, 0x01);
	}
}
#endif				/* CONFIG_IDE */


#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
	return dm9000_initialize(bis);
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
6d33c6ac TL	2	/*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
32dbaafa	6	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6d33c6ac	7	* Hayden Fraser (Hayden.Fraser@freescale.com)
6d33c6ac TL	8	*/
	9
	10	#include <common.h>
49acd56e	11	#include <init.h>
90526e9f	12	#include <net.h>
6d33c6ac	13	#include <asm/immap.h>
60f61e6d	14	#include <netdev.h>
6752da6b	15	#include <asm/io.h>
6d33c6ac	16
088454cd SG	17	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	18
6d33c6ac TL	19	int checkboard(void)
	20	{
	21	puts("Board: ");
	22	puts("Freescale MCF5253 DEMO\n");
	23	return 0;
	24	};
	25
f1683aa7	26	int dram_init(void)
6d33c6ac TL	27	{
	28	u32 dramsize = 0;
	29
	30	/*
	31	* Check to see if the SDRAM has already been initialized
	32	* by a run control tool
	33	*/
	34	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
	35	u32 RC, temp;
	36
6d0f6bcf	37	RC = (CONFIG_SYS_CLK / 1000000) >> 1;
6d33c6ac TL	38	RC = (RC * 15) >> 4;
	39
	40	/* Initialize DRAM Control Register: DCR */
	41	mbar_writeShort(MCFSIM_DCR, (0x8400 \| RC));
	42	__asm__("nop");
	43
	44	mbar_writeLong(MCFSIM_DACR0, 0x00003224);
	45	__asm__("nop");
	46
	47	/* Initialize DMR0 */
6d0f6bcf	48	dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
6d33c6ac TL	49	temp = (dramsize - 1) & 0xFFFC0000;
	50	mbar_writeLong(MCFSIM_DMR0, temp \| 1);
	51	__asm__("nop");
	52
	53	mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
6752da6b	54	mb();
6d33c6ac TL	55	__asm__("nop");
	56
	57	/* Write to this block to initiate precharge */
6d0f6bcf	58	(u32 ) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
6752da6b	59	mb();
6d33c6ac TL	60	__asm__("nop");
	61
	62	/* Set RE bit in DACR */
	63	mbar_writeLong(MCFSIM_DACR0,
	64	mbar_readLong(MCFSIM_DACR0) \| 0x8000);
	65	__asm__("nop");
	66
	67	/* Wait for at least 8 auto refresh cycles to occur */
	68	udelay(500);
	69
	70	/* Finish the configuration by issuing the MRS */
	71	mbar_writeLong(MCFSIM_DACR0,
	72	mbar_readLong(MCFSIM_DACR0) \| 0x0040);
	73	__asm__("nop");
	74
6d0f6bcf	75	(u32 ) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
6752da6b	76	mb();
6d33c6ac TL	77	}
6d33c6ac TL	78
088454cd SG	79	gd->ram_size = dramsize;
	80
	81	return 0;
6d33c6ac TL	82	}
	83
	84	int testdram(void)
	85	{
	86	/* TODO: XXX XXX XXX */
	87	printf("DRAM test not implemented!\n");
	88
	89	return (0);
	90	}
	91
fc843a02	92	#ifdef CONFIG_IDE
6d33c6ac TL	93	#include <ata.h>
	94	int ide_preinit(void)
	95	{
	96	return (0);
	97	}
	98
	99	void ide_set_reset(int idereset)
	100	{
32dbaafa	101	atac_t ata = (atac_t ) CONFIG_SYS_ATA_BASE_ADDR;
6d33c6ac TL	102	long period;
	103	/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
	104	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
	105	{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
	106	{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
	107	{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
	108	{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
	109	};
	110
	111	if (idereset) {
32dbaafa AW	112	/* control reset */
32dbaafa AW	113	out_8(&ata->cr, 0);
6d33c6ac TL	114	udelay(100);
	115	} else {
	116	mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
	117
	118	#define CALC_TIMING(t) (t + period - 1) / period
6d0f6bcf	119	period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
6d33c6ac TL	120
6d33c6ac TL	121	/ata->ton = CALC_TIMING (180); /
32dbaafa AW	122	out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
	123	out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
	124	out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
	125	out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
	126	out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
	127	out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
	128	out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
	129
	130	/* IORDY enable */
	131	out_8(&ata->cr, 0x40);
6d33c6ac	132	udelay(2000);
32dbaafa AW	133	/* IORDY enable */
32dbaafa AW	134	setbits_8(&ata->cr, 0x01);
6d33c6ac TL	135	}
6d33c6ac TL	136	}
fc843a02	137	#endif /* CONFIG_IDE */
60f61e6d RB	138
	139
	140	#ifdef CONFIG_DRIVER_DM9000
	141	int board_eth_init(bd_t *bis)
	142	{
	143	return dm9000_initialize(bis);
	144	}
	145	#endif