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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / board / freescale / mpc5121ads / mpc5121ads.c
CommitLineData
8993e54b 1/*
843efb11 2 * (C) Copyright 2007-2009 DENX Software Engineering
8993e54b
RJ		 3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <common.h>
8993e54b
RJ		 25#include <asm/bitops.h>
26#include <command.h>
843efb11 27#include <asm/io.h>
8a490422 28#include <asm/processor.h>
7629f1c0 29#include <asm/mpc512x.h>
e343ab83 30#include <fdt_support.h>
f31c49db
MM		 31#ifdef CONFIG_MISC_INIT_R
32#include <i2c.h>
33#endif
a5aa3998 34#include <net.h>
9b55a253 35
229549a5
SR		 36#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38
70a4da45
RK		 39DECLARE_GLOBAL_DATA_PTR;
40
229549a5
SR		 41void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
42
43/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
44extern int mpc5121_nfc_chip;
45
46/* Control chips select signal on MPC5121ADS board */
47void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
48{
49 unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
50 u8 v;
51
52 v = in_8(csreg);
53 v |= 0x0F;
54
55 if (chip >= 0) {
56 __mpc5121_nfc_select_chip(mtd, 0);
57 v &= ~(1 << mpc5121_nfc_chip);
58 } else {
59 __mpc5121_nfc_select_chip(mtd, -1);
60 }
61
62 out_8(csreg, v);
63}
8993e54b 64
7629f1c0 65int board_early_init_f(void)
8993e54b 66{
8993e54b
RJ		 67 /*
68 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
69 *
70 * Without this the flash identification routine fails, as it needs to issue
71 * write commands in order to establish the device ID.
72 */
8993e54b 73
812493ad 74#ifdef CONFIG_MPC5121ADS_REV2
843efb11 75 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
f31c49db 76#else
843efb11
WD		 77 if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
78 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
f31c49db
MM		 79 } else {
80 /* running from Backup flash */
843efb11 81 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
f31c49db
MM		 82 }
83#endif
8993e54b
RJ		 84 return 0;
85}
86
a5aa3998
MS		 87int is_micron(void){
88
89 ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
90 uchar macaddr[6];
91 u32 brddate, macchk, ismicron;
92
93 /*
94 * MAC address has serial number with date of manufacture
95 * Boards made before Nov-08 #1180 use Micron memory;
96 * 001e59 is the STx vendor #
97 * Default is Elpida since it works for both but is slightly slower
98 */
99 ismicron = 0;
100 if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
101 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
102 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
103 debug("brddate = %d\n\t", brddate);
104
105 if (macchk == 0x001e59 && brddate <= 8111180)
106 ismicron = 1;
107 } else if (brd_rev < 0x400) {
108 ismicron = 1;
109 }
110 debug("Using %s Memory settings\n\t",
111 ismicron ? "Micron" : "Elpida");
112 return(ismicron);
113}
114
7629f1c0 115phys_size_t initdram(int board_type)
8993e54b
RJ		 116{
117 u32 msize = 0;
a5aa3998
MS		 118 /*
119 * Elpida MDDRC and initialization settings are an alternative
120 * to the Default Micron ones for all but the earliest Rev 4 boards
121 */
da01f534
WD		 122 ddr512x_config_t elpida_mddrc_config = {
123 .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
124 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
125 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
126 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
a5aa3998
MS		 127 };
128
129 u32 elpida_init_sequence[] = {
130 CONFIG_SYS_DDRCMD_NOP,
131 CONFIG_SYS_DDRCMD_NOP,
132 CONFIG_SYS_DDRCMD_NOP,
133 CONFIG_SYS_DDRCMD_NOP,
134 CONFIG_SYS_DDRCMD_NOP,
135 CONFIG_SYS_DDRCMD_NOP,
136 CONFIG_SYS_DDRCMD_NOP,
137 CONFIG_SYS_DDRCMD_NOP,
138 CONFIG_SYS_DDRCMD_NOP,
139 CONFIG_SYS_DDRCMD_NOP,
140 CONFIG_SYS_DDRCMD_PCHG_ALL,
141 CONFIG_SYS_DDRCMD_NOP,
142 CONFIG_SYS_DDRCMD_RFSH,
143 CONFIG_SYS_DDRCMD_NOP,
144 CONFIG_SYS_DDRCMD_RFSH,
145 CONFIG_SYS_DDRCMD_NOP,
146 CONFIG_SYS_DDRCMD_EM2,
147 CONFIG_SYS_DDRCMD_EM3,
148 CONFIG_SYS_DDRCMD_EN_DLL,
149 CONFIG_SYS_ELPIDA_RES_DLL,
150 CONFIG_SYS_DDRCMD_PCHG_ALL,
151 CONFIG_SYS_DDRCMD_RFSH,
152 CONFIG_SYS_DDRCMD_RFSH,
153 CONFIG_SYS_DDRCMD_RFSH,
154 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
155 CONFIG_SYS_DDRCMD_NOP,
156 CONFIG_SYS_DDRCMD_NOP,
157 CONFIG_SYS_DDRCMD_NOP,
158 CONFIG_SYS_DDRCMD_NOP,
159 CONFIG_SYS_DDRCMD_NOP,
160 CONFIG_SYS_DDRCMD_NOP,
161 CONFIG_SYS_DDRCMD_NOP,
162 CONFIG_SYS_DDRCMD_NOP,
163 CONFIG_SYS_DDRCMD_NOP,
164 CONFIG_SYS_DDRCMD_NOP,
165 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
166 CONFIG_SYS_ELPIDA_OCD_EXIT,
167 CONFIG_SYS_DDRCMD_NOP,
168 CONFIG_SYS_DDRCMD_NOP,
169 CONFIG_SYS_DDRCMD_NOP,
170 CONFIG_SYS_DDRCMD_NOP,
171 CONFIG_SYS_DDRCMD_NOP,
172 CONFIG_SYS_DDRCMD_NOP,
173 CONFIG_SYS_DDRCMD_NOP,
174 CONFIG_SYS_DDRCMD_NOP,
175 CONFIG_SYS_DDRCMD_NOP,
176 CONFIG_SYS_DDRCMD_NOP
177 };
178
179 if (is_micron()) {
180 msize = fixed_sdram(NULL, NULL, 0);
181 } else {
da01f534 182 msize = fixed_sdram(&elpida_mddrc_config,
a5aa3998
MS		 183 elpida_init_sequence,
184 sizeof(elpida_init_sequence)/sizeof(u32));
185 }
8993e54b
RJ		 186
187 return msize;
188}
189
0e1bad47
YS		 190int misc_init_r(void)
191{
192 u8 tmp_val;
193
194 /* Using this for DIU init before the driver in linux takes over
195 * Enable the TFP410 Encoder (I2C address 0x38)
196 */
197
198 i2c_set_bus_num(2);
199 tmp_val = 0xBF;
200 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
201 /* Verify if enabled */
202 tmp_val = 0;
203 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
dffe06fa 204 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
0e1bad47
YS		 205
206 tmp_val = 0x10;
207 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
208 /* Verify if enabled */
209 tmp_val = 0;
210 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
dffe06fa 211 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
0e1bad47 212
0e1bad47
YS		 213 return 0;
214}
72601d04 215
6689484c
KJ		 216static iopin_t ioregs_init[] = {
217 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
218 {
843efb11 219 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
6689484c
KJ		 220 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
221 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
222 },
223 /* Set highest Slew on 9 PATA pins */
224 {
843efb11 225 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
6689484c
KJ		 226 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
227 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
228 },
229 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
230 {
843efb11 231 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
6689484c
KJ		 232 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
233 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
234 },
235 /* FUNC1=SPDIF_TXCLK */
236 {
843efb11 237 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
6689484c
KJ		 238 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
239 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
240 },
241 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
242 {
843efb11 243 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
6689484c
KJ		 244 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
245 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
246 },
247 /* FUNC2=DIU CLK */
248 {
843efb11 249 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
6689484c
KJ		 250 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
251 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
252 },
253 /* FUNC2=DIU_HSYNC */
254 {
843efb11 255 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
6689484c
KJ		 256 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
257 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
258 },
259 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
260 {
843efb11 261 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
6689484c
KJ		 262 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
263 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
264 }
265};
0e1bad47 266
14d19cd1
JR		 267static iopin_t rev2_silicon_pci_ioregs_init[] = {
268 /* FUNC0=PCI Sets next 54 to PCI pads */
269 {
843efb11 270 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
14d19cd1
JR		 271 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
272 }
273};
274
8993e54b
RJ		 275int checkboard (void)
276{
6d0f6bcf
JCPV		 277 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
278 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
14d19cd1 279 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
843efb11 280 u32 spridr = in_be32(&im->sysconf.spridr);
8993e54b 281
812493ad 282 printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
b1b54e35 283 brd_rev, cpld_rev);
72601d04 284
16bee7b0 285 /* initialize function mux & slew rate IO inter alia on IO Pins */
72601d04 286 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
6689484c 287
843efb11 288 if (SVR_MJREV (spridr) >= 2)
14d19cd1 289 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
51b67d06 290
8993e54b
RJ		 291 return 0;
292}
281ff9a4
GB		 293
294#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
295void ft_board_setup(void *blob, bd_t *bd)
296{
297 ft_cpu_setup(blob, bd);
281ff9a4
GB		 298}
299#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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