[people/ms/u-boot.git] / board / freescale / mpc8308rdb / mpc8308rdb.c

/*
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
#include <spi.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * The following are used to control the SPI chip selects for the SPI command.
 */
#ifdef CONFIG_MPC8XXX_SPI

#define SPI_CS_MASK	0x00400000

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

	/* active low */
	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

	/* inactive high */
	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
}
#endif /* CONFIG_MPC8XXX_SPI */

#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bd)
{
	return fsl_esdhc_mmc_init(bd);
}
#endif

static u8 read_board_info(void)
{
	u8 val8;
	i2c_set_bus_num(0);

	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
		return val8;
	else
		return 0;
}

int checkboard(void)
{
	static const char * const rev_str[] = {
		"1.0",
		"<reserved>",
		"<reserved>",
		"<reserved>",
		"<unknown>",
	};
	u8 info;
	int i;

	info = read_board_info();
	i = (!info) ? 4 : info & 0x03;

	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);

	return 0;
}

static struct pci_region pcie_regions_0[] = {
	{
		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
		.size = CONFIG_SYS_PCIE1_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

void pci_init_board(void)
{
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	sysconf83xx_t *sysconf = &immr->sysconf;
	law83xx_t *pcie_law = sysconf->pcielaw;
	struct pci_region *pcie_reg[] = { pcie_regions_0 };

	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);

	/* Deassert the resets in the control register */
	out_be32(&sysconf->pecr1, 0xE0008000);
	udelay(2000);

	/* Configure PCI Express Local Access Windows */
	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);

	mpc83xx_pcie_init(1, pcie_reg);
}
/*
 * Miscellaneous late-boot configurations
 *
 * If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
#ifdef CONFIG_MPC8XXX_SPI
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	sysconf83xx_t *sysconf = &immr->sysconf;

	/*
	 * Set proper bits in SICRH to allow SPI on header J8
	 *
	 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
	 * switch. The pinmux configuration does not have a fine enough
	 * granularity to support both simultaneously.
	 */
	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
	puts("WARNING: SPI enabled, TSEC2 support is broken\n");

	/* Set header J8 SPI chip select output, disabled */
	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
#endif

#ifdef CONFIG_VSC7385_IMAGE
	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
		CONFIG_VSC7385_IMAGE_SIZE)) {
		puts("Failure uploading VSC7385 microcode.\n");
		return 1;
	}
#endif

	return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
	fsl_fdt_fixup_dr_usb(blob, bd);
	fdt_fixup_esdhc(blob, bd);

	return 0;
}
#endif

int board_eth_init(bd_t *bis)
{
	int rv, num_if = 0;

	/* Initialize TSECs first */
	rv = cpu_eth_init(bis);
	if (rv >= 0)
		num_if += rv;
	else
		printf("ERROR: failed to initialize TSECs.\n");

	rv = pci_eth_init(bis);
	if (rv >= 0)
		num_if += rv;
	else
		printf("ERROR: failed to initialize PCI Ethernet.\n");

	return num_if;
}
Commit	Line	Data
5fb17030 IY	1	/*
	2	* Copyright (C) 2010 Freescale Semiconductor, Inc.
	3	* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5fb17030 IY	6	*/
	7
	8	#include <common.h>
	9	#include <hwconfig.h>
	10	#include <i2c.h>
ea1ea54e	11	#include <spi.h>
5fb17030 IY	12	#include <libfdt.h>
	13	#include <fdt_support.h>
	14	#include <pci.h>
	15	#include <mpc83xx.h>
	16	#include <vsc7385.h>
	17	#include <netdev.h>
db1fc7d2	18	#include <fsl_esdhc.h>
5fb17030 IY	19	#include <asm/io.h>
	20	#include <asm/fsl_serdes.h>
	21	#include <asm/fsl_mpc83xx_serdes.h>
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
ea1ea54e IS	25	/*
	26	* The following are used to control the SPI chip selects for the SPI command.
	27	*/
	28	#ifdef CONFIG_MPC8XXX_SPI
	29
	30	#define SPI_CS_MASK 0x00400000
	31
	32	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	33	{
	34	return bus == 0 && cs == 0;
	35	}
	36
	37	void spi_cs_activate(struct spi_slave *slave)
	38	{
	39	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	40
	41	/* active low */
	42	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
	43	}
	44
	45	void spi_cs_deactivate(struct spi_slave *slave)
	46	{
	47	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	48
	49	/* inactive high */
	50	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
	51	}
	52	#endif /* CONFIG_MPC8XXX_SPI */
	53
db1fc7d2 IS	54	#ifdef CONFIG_FSL_ESDHC
	55	int board_mmc_init(bd_t *bd)
	56	{
	57	return fsl_esdhc_mmc_init(bd);
	58	}
	59	#endif
	60
5fb17030 IY	61	static u8 read_board_info(void)
	62	{
	63	u8 val8;
	64	i2c_set_bus_num(0);
	65
	66	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
	67	return val8;
	68	else
	69	return 0;
	70	}
	71
	72	int checkboard(void)
	73	{
	74	static const char * const rev_str[] = {
	75	"1.0",
	76	"<reserved>",
	77	"<reserved>",
	78	"<reserved>",
	79	"<unknown>",
	80	};
	81	u8 info;
	82	int i;
	83
	84	info = read_board_info();
	85	i = (!info) ? 4 : info & 0x03;
	86
	87	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
	88
	89	return 0;
	90	}
	91
	92	static struct pci_region pcie_regions_0[] = {
	93	{
	94	.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
	95	.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
	96	.size = CONFIG_SYS_PCIE1_MEM_SIZE,
	97	.flags = PCI_REGION_MEM,
	98	},
	99	{
	100	.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
	101	.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
	102	.size = CONFIG_SYS_PCIE1_IO_SIZE,
	103	.flags = PCI_REGION_IO,
	104	},
	105	};
	106
	107	void pci_init_board(void)
	108	{
	109	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	110	sysconf83xx_t *sysconf = &immr->sysconf;
5fb17030 IY	111	law83xx_t *pcie_law = sysconf->pcielaw;
	112	struct pci_region *pcie_reg[] = { pcie_regions_0 };
	113
	114	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
	115	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	116
5fb17030 IY	117	/* Deassert the resets in the control register */
	118	out_be32(&sysconf->pecr1, 0xE0008000);
	119	udelay(2000);
	120
	121	/* Configure PCI Express Local Access Windows */
	122	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	123	out_be32(&pcie_law[0].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	124
6aa3d3bf	125	mpc83xx_pcie_init(1, pcie_reg);
5fb17030 IY	126	}
	127	/*
	128	* Miscellaneous late-boot configurations
	129	*
	130	* If a VSC7385 microcode image is present, then upload it.
	131	*/
	132	int misc_init_r(void)
	133	{
ea1ea54e IS	134	#ifdef CONFIG_MPC8XXX_SPI
	135	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
	136	sysconf83xx_t *sysconf = &immr->sysconf;
	137
	138	/*
	139	* Set proper bits in SICRH to allow SPI on header J8
	140	*
	141	* NOTE: this breaks the TSEC2 interface, attached to the Vitesse
	142	* switch. The pinmux configuration does not have a fine enough
	143	* granularity to support both simultaneously.
	144	*/
	145	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
	146	puts("WARNING: SPI enabled, TSEC2 support is broken\n");
	147
	148	/* Set header J8 SPI chip select output, disabled */
	149	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
	150	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
	151	#endif
	152
5fb17030 IY	153	#ifdef CONFIG_VSC7385_IMAGE
	154	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
	155	CONFIG_VSC7385_IMAGE_SIZE)) {
	156	puts("Failure uploading VSC7385 microcode.\n");
	157	return 1;
	158	}
	159	#endif
	160
	161	return 0;
	162	}
	163	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	164	int ft_board_setup(void blob, bd_t bd)
5fb17030 IY	165	{
5fb17030 IY	166	ft_cpu_setup(blob, bd);
a5c289b9	167	fsl_fdt_fixup_dr_usb(blob, bd);
db1fc7d2	168	fdt_fixup_esdhc(blob, bd);
e895a4b0 SG	169
e895a4b0 SG	170	return 0;
5fb17030 IY	171	}
	172	#endif
	173
	174	int board_eth_init(bd_t *bis)
	175	{
	176	int rv, num_if = 0;
	177
	178	/* Initialize TSECs first */
65ea7589 IY	179	rv = cpu_eth_init(bis);
65ea7589 IY	180	if (rv >= 0)
5fb17030 IY	181	num_if += rv;
	182	else
	183	printf("ERROR: failed to initialize TSECs.\n");
	184
65ea7589 IY	185	rv = pci_eth_init(bis);
65ea7589 IY	186	if (rv >= 0)
5fb17030 IY	187	num_if += rv;
	188	else
	189	printf("ERROR: failed to initialize PCI Ethernet.\n");
	190
	191	return num_if;
	192	}