[thirdparty/u-boot.git] / board / freescale / mpc8315erdb / mpc8315erdb.c

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * Author: Scott Wood <scottwood@freescale.com>
 *         Dave Liu <daveliu@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
#include <ns16550.h>
#include <nand.h>

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;

	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
		gd->flags |= GD_FLG_SILENT;

	return 0;
}

#ifndef CONFIG_NAND_SPL

static u8 read_board_info(void)
{
	u8 val8;
	i2c_set_bus_num(0);

	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
		return val8;
	else
		return 0;
}

int checkboard(void)
{
	static const char * const rev_str[] = {
		"0.0",
		"0.1",
		"1.0",
		"1.1",
		"<unknown>",
	};
	u8 info;
	int i;

	info = read_board_info();
	i = (!info) ? 4: info & 0x03;

	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);

	return 0;
}

static struct pci_region pci_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI_MEM_BASE,
		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
		size: CONFIG_SYS_PCI_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
		size: CONFIG_SYS_PCI_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
	{
		bus_start: CONFIG_SYS_PCI_IO_BASE,
		phys_start: CONFIG_SYS_PCI_IO_PHYS,
		size: CONFIG_SYS_PCI_IO_SIZE,
		flags: PCI_REGION_IO
	}
};

static struct pci_region pcie_regions_0[] = {
	{
		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
		.size = CONFIG_SYS_PCIE1_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

static struct pci_region pcie_regions_1[] = {
	{
		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
		.size = CONFIG_SYS_PCIE2_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

void pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile sysconf83xx_t *sysconf = &immr->sysconf;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	volatile law83xx_t *pcie_law = sysconf->pcielaw;
	struct pci_region *reg[] = { pci_regions };
	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };

	/* Enable all 3 PCI_CLK_OUTPUTs. */
	clk->occr |= 0xe0000000;

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;

	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;

	mpc83xx_pci_init(1, reg);

	/* Configure the clock for PCIE controller */
	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);

	/* Deassert the resets in the control register */
	out_be32(&sysconf->pecr1, 0xE0008000);
	out_be32(&sysconf->pecr2, 0xE0008000);
	udelay(2000);

	/* Configure PCI Express Local Access Windows */
	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);

	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);

	mpc83xx_pcie_init(2, pcie_reg);
}

#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_tsec1_fixup(void *fdt, bd_t *bd)
{
	const char disabled[] = "disabled";
	const char *path;
	int ret;

	if (hwconfig_arg_cmp("board_type", "tsec1")) {
		return;
	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
		printf("NOTICE: No or unknown board_type hwconfig specified.\n"
		       "        Assuming board with TSEC1.\n");
		return;
	}

	ret = fdt_path_offset(fdt, "/aliases");
	if (ret < 0) {
		printf("WARNING: can't find /aliases node\n");
		return;
	}

	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
	if (!path) {
		printf("WARNING: can't find ethernet0 alias\n");
		return;
	}

	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
}

int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	fsl_fdt_fixup_dr_usb(blob, bd);
	fdt_tsec1_fixup(blob, bd);

	return 0;
}
#endif

int board_eth_init(bd_t *bis)
{
	cpu_eth_init(bis);	/* Initialize TSECs first */
	return pci_eth_init(bis);
}

#else /* CONFIG_NAND_SPL */

int checkboard(void)
{
	puts("Board: Freescale MPC8315ERDB\n");
	return 0;
}

void board_init_f(ulong bootflag)
{
	board_early_init_f();
	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
	puts("NAND boot... ");
	timer_init();
	dram_init();
	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
		      CONFIG_SYS_NAND_U_BOOT_RELOC);
}

void board_init_r(gd_t *gd, ulong dest_addr)
{
	nand_boot();
}

void putc(char c)
{
	if (gd->flags & GD_FLG_SILENT)
		return;

	if (c == '\n')
		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');

	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}

#endif /* CONFIG_NAND_SPL */
Commit	Line	Data
8bd522ce DL	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Scott Wood <scottwood@freescale.com>
	5	* Dave Liu <daveliu@freescale.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
8bd522ce DL	8	*/
	9
	10	#include <common.h>
b8b71ffb	11	#include <hwconfig.h>
8bd522ce	12	#include <i2c.h>
b08c8c48	13	#include <linux/libfdt.h>
25f5f0d4	14	#include <fdt_support.h>
8bd522ce DL	15	#include <pci.h>
8bd522ce DL	16	#include <mpc83xx.h>
10efa024	17	#include <netdev.h>
8f11e34b	18	#include <asm/io.h>
2e95004d AV	19	#include <ns16550.h>
2e95004d AV	20	#include <nand.h>
8bd522ce DL	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
	24	int board_early_init_f(void)
	25	{
6d0f6bcf	26	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
8bd522ce DL	27
	28	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
	29	gd->flags \|= GD_FLG_SILENT;
	30
	31	return 0;
	32	}
	33
2e95004d AV	34	#ifndef CONFIG_NAND_SPL
2e95004d AV	35
8bd522ce DL	36	static u8 read_board_info(void)
	37	{
	38	u8 val8;
	39	i2c_set_bus_num(0);
	40
6d0f6bcf	41	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
8bd522ce DL	42	return val8;
	43	else
	44	return 0;
	45	}
	46
	47	int checkboard(void)
	48	{
	49	static const char * const rev_str[] = {
	50	"0.0",
	51	"0.1",
	52	"1.0",
	53	"1.1",
	54	"<unknown>",
	55	};
	56	u8 info;
	57	int i;
	58
	59	info = read_board_info();
	60	i = (!info) ? 4: info & 0x03;
	61
	62	printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
	63
	64	return 0;
	65	}
	66
	67	static struct pci_region pci_regions[] = {
	68	{
6d0f6bcf JCPV	69	bus_start: CONFIG_SYS_PCI_MEM_BASE,
	70	phys_start: CONFIG_SYS_PCI_MEM_PHYS,
	71	size: CONFIG_SYS_PCI_MEM_SIZE,
8bd522ce DL	72	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	73	},
	74	{
6d0f6bcf JCPV	75	bus_start: CONFIG_SYS_PCI_MMIO_BASE,
	76	phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
	77	size: CONFIG_SYS_PCI_MMIO_SIZE,
8bd522ce DL	78	flags: PCI_REGION_MEM
	79	},
	80	{
6d0f6bcf JCPV	81	bus_start: CONFIG_SYS_PCI_IO_BASE,
	82	phys_start: CONFIG_SYS_PCI_IO_PHYS,
	83	size: CONFIG_SYS_PCI_IO_SIZE,
8bd522ce DL	84	flags: PCI_REGION_IO
	85	}
	86	};
	87
8f11e34b AV	88	static struct pci_region pcie_regions_0[] = {
	89	{
	90	.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
	91	.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
	92	.size = CONFIG_SYS_PCIE1_MEM_SIZE,
	93	.flags = PCI_REGION_MEM,
	94	},
	95	{
	96	.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
	97	.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
	98	.size = CONFIG_SYS_PCIE1_IO_SIZE,
	99	.flags = PCI_REGION_IO,
	100	},
	101	};
	102
	103	static struct pci_region pcie_regions_1[] = {
	104	{
	105	.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
	106	.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
	107	.size = CONFIG_SYS_PCIE2_MEM_SIZE,
	108	.flags = PCI_REGION_MEM,
	109	},
	110	{
	111	.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
	112	.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
	113	.size = CONFIG_SYS_PCIE2_IO_SIZE,
	114	.flags = PCI_REGION_IO,
	115	},
	116	};
	117
8bd522ce DL	118	void pci_init_board(void)
8bd522ce DL	119	{
6d0f6bcf	120	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
8f11e34b	121	volatile sysconf83xx_t *sysconf = &immr->sysconf;
8bd522ce DL	122	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
8bd522ce DL	123	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
8f11e34b	124	volatile law83xx_t *pcie_law = sysconf->pcielaw;
8bd522ce	125	struct pci_region *reg[] = { pci_regions };
8f11e34b	126	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
8bd522ce DL	127
	128	/* Enable all 3 PCI_CLK_OUTPUTs. */
	129	clk->occr \|= 0xe0000000;
	130
	131	/*
	132	* Configure PCI Local Access Windows
	133	*/
6d0f6bcf	134	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
8bd522ce DL	135	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
8bd522ce DL	136
6d0f6bcf	137	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
8bd522ce DL	138	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
8bd522ce DL	139
6aa3d3bf	140	mpc83xx_pci_init(1, reg);
8f11e34b AV	141
	142	/* Configure the clock for PCIE controller */
	143	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM \| SCCR_PCIEXP2CM,
	144	SCCR_PCIEXP1CM_1 \| SCCR_PCIEXP2CM_1);
	145
	146	/* Deassert the resets in the control register */
	147	out_be32(&sysconf->pecr1, 0xE0008000);
	148	out_be32(&sysconf->pecr2, 0xE0008000);
	149	udelay(2000);
	150
	151	/* Configure PCI Express Local Access Windows */
	152	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	153	out_be32(&pcie_law[0].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	154
	155	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	156	out_be32(&pcie_law[1].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	157
6aa3d3bf	158	mpc83xx_pcie_init(2, pcie_reg);
8bd522ce DL	159	}
	160
	161	#if defined(CONFIG_OF_BOARD_SETUP)
25f5f0d4 AV	162	void fdt_tsec1_fixup(void fdt, bd_t bd)
25f5f0d4 AV	163	{
25f5f0d4 AV	164	const char disabled[] = "disabled";
	165	const char *path;
	166	int ret;
	167
b8b71ffb	168	if (hwconfig_arg_cmp("board_type", "tsec1")) {
021f6df6	169	return;
b8b71ffb AV	170	} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
	171	printf("NOTICE: No or unknown board_type hwconfig specified.\n"
	172	" Assuming board with TSEC1.\n");
021f6df6	173	return;
25f5f0d4 AV	174	}
	175
	176	ret = fdt_path_offset(fdt, "/aliases");
	177	if (ret < 0) {
	178	printf("WARNING: can't find /aliases node\n");
	179	return;
	180	}
	181
	182	path = fdt_getprop(fdt, ret, "ethernet0", NULL);
	183	if (!path) {
	184	printf("WARNING: can't find ethernet0 alias\n");
	185	return;
	186	}
	187
	188	do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
	189	}
	190
e895a4b0	191	int ft_board_setup(void blob, bd_t bd)
8bd522ce DL	192	{
	193	ft_cpu_setup(blob, bd);
	194	#ifdef CONFIG_PCI
	195	ft_pci_setup(blob, bd);
	196	#endif
a5c289b9	197	fsl_fdt_fixup_dr_usb(blob, bd);
25f5f0d4	198	fdt_tsec1_fixup(blob, bd);
e895a4b0 SG	199
e895a4b0 SG	200	return 0;
8bd522ce DL	201	}
8bd522ce DL	202	#endif
10efa024 BW	203
	204	int board_eth_init(bd_t *bis)
	205	{
	206	cpu_eth_init(bis); /* Initialize TSECs first */
	207	return pci_eth_init(bis);
	208	}
2e95004d AV	209
	210	#else /* CONFIG_NAND_SPL */
	211
	212	int checkboard(void)
	213	{
	214	puts("Board: Freescale MPC8315ERDB\n");
	215	return 0;
	216	}
	217
	218	void board_init_f(ulong bootflag)
	219	{
	220	board_early_init_f();
	221	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
	222	CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
	223	puts("NAND boot... ");
70e2aaf3	224	timer_init();
f1683aa7	225	dram_init();
2e95004d AV	226	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
	227	CONFIG_SYS_NAND_U_BOOT_RELOC);
	228	}
	229
	230	void board_init_r(gd_t *gd, ulong dest_addr)
	231	{
	232	nand_boot();
	233	}
	234
	235	void putc(char c)
	236	{
	237	if (gd->flags & GD_FLG_SILENT)
	238	return;
	239
	240	if (c == '\n')
	241	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
	242
	243	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
	244	}
	245
	246	#endif /* CONFIG_NAND_SPL */