[thirdparty/u-boot.git] / board / freescale / mpc8323erdb / mpc8323erdb.c

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * Michael Barkowski <michael.barkowski@freescale.com>
 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <common.h>
#include <eeprom.h>
#include <env.h>
#include <init.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <command.h>
#include <linux/libfdt.h>
#include <u-boot/crc.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#include <asm/mmu.h>

DECLARE_GLOBAL_DATA_PTR;

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* UCC3 */
	{1,  0, 1, 0, 1}, /* TxD0 */
	{1,  1, 1, 0, 1}, /* TxD1 */
	{1,  2, 1, 0, 1}, /* TxD2 */
	{1,  3, 1, 0, 1}, /* TxD3 */
	{1,  9, 1, 0, 1}, /* TxER */
	{1, 12, 1, 0, 1}, /* TxEN */
	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */

	{1,  4, 2, 0, 1}, /* RxD0 */
	{1,  5, 2, 0, 1}, /* RxD1 */
	{1,  6, 2, 0, 1}, /* RxD2 */
	{1,  7, 2, 0, 1}, /* RxD3 */
	{1,  8, 2, 0, 1}, /* RxER */
	{1, 10, 2, 0, 1}, /* RxDV */
	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
	{1, 11, 2, 0, 1}, /* COL */
	{1, 13, 2, 0, 1}, /* CRS */

	/* UCC2 */
	{0, 18, 1, 0, 1}, /* TxD0 */
	{0, 19, 1, 0, 1}, /* TxD1 */
	{0, 20, 1, 0, 1}, /* TxD2 */
	{0, 21, 1, 0, 1}, /* TxD3 */
	{0, 27, 1, 0, 1}, /* TxER */
	{0, 30, 1, 0, 1}, /* TxEN */
	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */

	{0, 22, 2, 0, 1}, /* RxD0 */
	{0, 23, 2, 0, 1}, /* RxD1 */
	{0, 24, 2, 0, 1}, /* RxD2 */
	{0, 25, 2, 0, 1}, /* RxD3 */
	{0, 26, 1, 0, 1}, /* RxER */
	{0, 28, 2, 0, 1}, /* Rx_DV */
	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
	{0, 29, 2, 0, 1}, /* COL */
	{0, 31, 2, 0, 1}, /* CRS */

	{3,  4, 3, 0, 2}, /* MDIO */
	{3,  5, 1, 0, 2}, /* MDC */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

int fixed_sdram(void);

int dram_init(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -ENXIO;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;

	msize = fixed_sdram();

	/* set total bus SDRAM size(bytes)  -- DDR */
	gd->ram_size = msize * 1024 * 1024;

	return 0;
}

/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CONFIG_SYS_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].ar =
	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	__asm__ __volatile__ ("sync");
	udelay(200);

	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	__asm__ __volatile__ ("sync");
	return msize;
}

int checkboard(void)
{
	puts("Board: Freescale MPC8323ERDB\n");
	return 0;
}

static struct pci_region pci_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
		size: CONFIG_SYS_PCI1_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
		size: CONFIG_SYS_PCI1_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
	{
		bus_start: CONFIG_SYS_PCI1_IO_BASE,
		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
		size: CONFIG_SYS_PCI1_IO_SIZE,
		flags: PCI_REGION_IO
	}
};

void pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	struct pci_region *reg[] = { pci_regions };

	/* Enable all 3 PCI_CLK_OUTPUTs. */
	clk->occr |= 0xe0000000;

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;

	mpc83xx_pci_init(1, reg);
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif

	return 0;
}
#endif

#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
int mac_read_from_eeprom(void)
{
	uchar buf[28];
	char str[18];
	int i = 0;
	unsigned int crc = 0;
	unsigned char enetvar[32];

	/* Read MAC addresses from EEPROM */
	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
		       CONFIG_SYS_I2C_EEPROM_ADDR);
	} else {
		uint32_t crc_buf;

		memcpy(&crc_buf, &buf[24], sizeof(uint32_t));

		if (crc32(crc, buf, 24) == crc_buf) {
			printf("Reading MAC from EEPROM\n");
			for (i = 0; i < 4; i++) {
				if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
					sprintf(str,
						"%02X:%02X:%02X:%02X:%02X:%02X",
						buf[i * 6], buf[i * 6 + 1],
						buf[i * 6 + 2], buf[i * 6 + 3],
						buf[i * 6 + 4], buf[i * 6 + 5]);
					sprintf((char *)enetvar,
						i ? "eth%daddr" : "ethaddr", i);
					env_set((char *)enetvar, str);
				}
			}
		}
	}
	return 0;
}
#endif				/* CONFIG_I2C_MAC_OFFSET */
Commit	Line	Data
1c274c4e KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* Michael Barkowski <michael.barkowski@freescale.com>
	5	* Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published
	9	* by the Free Software Foundation.
	10	*/
	11
	12	#include <common.h>
cb3ef681	13	#include <eeprom.h>
9fb625ce	14	#include <env.h>
2cf431c2	15	#include <init.h>
1c274c4e KP	16	#include <ioports.h>
	17	#include <mpc83xx.h>
	18	#include <i2c.h>
1c274c4e KP	19	#include <miiphy.h>
1c274c4e KP	20	#include <command.h>
b08c8c48	21	#include <linux/libfdt.h>
3db71108	22	#include <u-boot/crc.h>
1c274c4e KP	23	#if defined(CONFIG_PCI)
	24	#include <pci.h>
	25	#endif
1c274c4e	26	#include <asm/mmu.h>
1c274c4e	27
088454cd SG	28	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	29
1c274c4e KP	30	const qe_iop_conf_t qe_iop_conf_tab[] = {
	31	/* UCC3 */
	32	{1, 0, 1, 0, 1}, /* TxD0 */
	33	{1, 1, 1, 0, 1}, /* TxD1 */
	34	{1, 2, 1, 0, 1}, /* TxD2 */
	35	{1, 3, 1, 0, 1}, /* TxD3 */
	36	{1, 9, 1, 0, 1}, /* TxER */
	37	{1, 12, 1, 0, 1}, /* TxEN */
	38	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
	39
	40	{1, 4, 2, 0, 1}, /* RxD0 */
	41	{1, 5, 2, 0, 1}, /* RxD1 */
	42	{1, 6, 2, 0, 1}, /* RxD2 */
	43	{1, 7, 2, 0, 1}, /* RxD3 */
	44	{1, 8, 2, 0, 1}, /* RxER */
	45	{1, 10, 2, 0, 1}, /* RxDV */
	46	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
	47	{1, 11, 2, 0, 1}, /* COL */
	48	{1, 13, 2, 0, 1}, /* CRS */
	49
	50	/* UCC2 */
	51	{0, 18, 1, 0, 1}, /* TxD0 */
	52	{0, 19, 1, 0, 1}, /* TxD1 */
	53	{0, 20, 1, 0, 1}, /* TxD2 */
	54	{0, 21, 1, 0, 1}, /* TxD3 */
	55	{0, 27, 1, 0, 1}, /* TxER */
	56	{0, 30, 1, 0, 1}, /* TxEN */
	57	{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
	58
	59	{0, 22, 2, 0, 1}, /* RxD0 */
	60	{0, 23, 2, 0, 1}, /* RxD1 */
	61	{0, 24, 2, 0, 1}, /* RxD2 */
	62	{0, 25, 2, 0, 1}, /* RxD3 */
	63	{0, 26, 1, 0, 1}, /* RxER */
	64	{0, 28, 2, 0, 1}, /* Rx_DV */
	65	{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
	66	{0, 29, 2, 0, 1}, /* COL */
	67	{0, 31, 2, 0, 1}, /* CRS */
	68
	69	{3, 4, 3, 0, 2}, /* MDIO */
	70	{3, 5, 1, 0, 2}, /* MDC */
	71
	72	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	73	};
	74
1c274c4e KP	75	int fixed_sdram(void);
1c274c4e KP	76
f1683aa7	77	int dram_init(void)
1c274c4e	78	{
6d0f6bcf	79	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
1c274c4e KP	80	u32 msize = 0;
	81
	82	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
088454cd	83	return -ENXIO;
1c274c4e KP	84
1c274c4e KP	85	/* DDR SDRAM - Main SODIMM */
8a81bfd2	86	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
1c274c4e KP	87
	88	msize = fixed_sdram();
	89
088454cd SG	90	/* set total bus SDRAM size(bytes) -- DDR */
	91	gd->ram_size = msize * 1024 * 1024;
	92
	93	return 0;
1c274c4e KP	94	}
	95
	96	/*************************************************************************
	97	* fixed sdram init -- doesn't use serial presence detect.
	98	************************************************************************/
	99	int fixed_sdram(void)
	100	{
6d0f6bcf	101	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
1c274c4e KP	102	u32 msize = 0;
	103	u32 ddr_size;
	104	u32 ddr_size_log2;
	105
6d0f6bcf	106	msize = CONFIG_SYS_DDR_SIZE;
1c274c4e KP	107	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	108	(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
	109	if (ddr_size & 1) {
	110	return -1;
	111	}
	112	}
	113	im->sysconf.ddrlaw[0].ar =
	114	LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
6d0f6bcf JCPV	115	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
	116	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	117	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	118	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	119	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	120	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	121	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	122	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	123	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	124	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	125	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	126	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
1c274c4e KP	127	__asm__ __volatile__ ("sync");
	128	udelay(200);
	129
	130	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	131	__asm__ __volatile__ ("sync");
	132	return msize;
	133	}
	134
	135	int checkboard(void)
	136	{
	137	puts("Board: Freescale MPC8323ERDB\n");
	138	return 0;
	139	}
	140
	141	static struct pci_region pci_regions[] = {
	142	{
6d0f6bcf JCPV	143	bus_start: CONFIG_SYS_PCI1_MEM_BASE,
	144	phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
	145	size: CONFIG_SYS_PCI1_MEM_SIZE,
1c274c4e KP	146	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	147	},
	148	{
6d0f6bcf JCPV	149	bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
	150	phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
	151	size: CONFIG_SYS_PCI1_MMIO_SIZE,
1c274c4e KP	152	flags: PCI_REGION_MEM
	153	},
	154	{
6d0f6bcf JCPV	155	bus_start: CONFIG_SYS_PCI1_IO_BASE,
	156	phys_start: CONFIG_SYS_PCI1_IO_PHYS,
	157	size: CONFIG_SYS_PCI1_IO_SIZE,
1c274c4e KP	158	flags: PCI_REGION_IO
	159	}
	160	};
	161
	162	void pci_init_board(void)
	163	{
6d0f6bcf	164	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
1c274c4e KP	165	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
	166	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	167	struct pci_region *reg[] = { pci_regions };
	168
	169	/* Enable all 3 PCI_CLK_OUTPUTs. */
	170	clk->occr \|= 0xe0000000;
	171
	172	/* Configure PCI Local Access Windows */
6d0f6bcf	173	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
1c274c4e KP	174	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
1c274c4e KP	175
6d0f6bcf	176	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
1c274c4e KP	177	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
1c274c4e KP	178
6aa3d3bf	179	mpc83xx_pci_init(1, reg);
1c274c4e KP	180	}
	181
	182	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	183	int ft_board_setup(void blob, bd_t bd)
1c274c4e	184	{
1c274c4e	185	ft_cpu_setup(blob, bd);
1c274c4e KP	186	#ifdef CONFIG_PCI
	187	ft_pci_setup(blob, bd);
	188	#endif
e895a4b0 SG	189
e895a4b0 SG	190	return 0;
1c274c4e	191	}
3fde9e8b	192	#endif
5b2793a3	193
6d0f6bcf	194	#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
5b2793a3 MB	195	int mac_read_from_eeprom(void)
	196	{
	197	uchar buf[28];
	198	char str[18];
	199	int i = 0;
	200	unsigned int crc = 0;
	201	unsigned char enetvar[32];
	202
	203	/* Read MAC addresses from EEPROM */
6d0f6bcf	204	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
5b2793a3	205	printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
6d0f6bcf	206	CONFIG_SYS_I2C_EEPROM_ADDR);
5b2793a3	207	} else {
f4ea9f86 WD	208	uint32_t crc_buf;
	209
	210	memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
	211
	212	if (crc32(crc, buf, 24) == crc_buf) {
5b2793a3 MB	213	printf("Reading MAC from EEPROM\n");
	214	for (i = 0; i < 4; i++) {
	215	if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
	216	sprintf(str,
	217	"%02X:%02X:%02X:%02X:%02X:%02X",
	218	buf[i * 6], buf[i * 6 + 1],
	219	buf[i * 6 + 2], buf[i * 6 + 3],
	220	buf[i * 6 + 4], buf[i * 6 + 5]);
	221	sprintf((char *)enetvar,
	222	i ? "eth%daddr" : "ethaddr", i);
382bee57	223	env_set((char *)enetvar, str);
5b2793a3 MB	224	}
	225	}
	226	}
	227	}
	228	return 0;
	229	}
	230	#endif /* CONFIG_I2C_MAC_OFFSET */