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1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <ioports.h> | |
27 | #include <mpc83xx.h> | |
28 | #include <asm/mpc8349_pci.h> | |
29 | #include <i2c.h> | |
80ddd226 | 30 | #include <spi.h> |
991425fe | 31 | #include <miiphy.h> |
991425fe | 32 | #include <spd_sdram.h> |
a30a549a | 33 | |
b3458d2c | 34 | #if defined(CONFIG_OF_LIBFDT) |
3fde9e8b | 35 | #include <libfdt.h> |
bf0b542d KP |
36 | #endif |
37 | ||
991425fe MB |
38 | int fixed_sdram(void); |
39 | void sdram_init(void); | |
40 | ||
41 | #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) | |
42 | void ddr_enable_ecc(unsigned int dram_size); | |
43 | #endif | |
44 | ||
45 | int board_early_init_f (void) | |
46 | { | |
47 | volatile u8* bcsr = (volatile u8*)CFG_BCSR; | |
48 | ||
49 | /* Enable flash write */ | |
50 | bcsr[1] &= ~0x01; | |
51 | ||
8fe9bf61 KG |
52 | #ifdef CFG_USE_MPC834XSYS_USB_PHY |
53 | /* Use USB PHY on SYS board */ | |
54 | bcsr[5] |= 0x02; | |
55 | #endif | |
56 | ||
991425fe MB |
57 | return 0; |
58 | } | |
59 | ||
60 | #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) | |
61 | ||
62 | long int initdram (int board_type) | |
63 | { | |
d239d74b | 64 | volatile immap_t *im = (immap_t *)CFG_IMMR; |
991425fe MB |
65 | u32 msize = 0; |
66 | ||
67 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) | |
68 | return -1; | |
69 | ||
70 | /* DDR SDRAM - Main SODIMM */ | |
71 | im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; | |
72 | #if defined(CONFIG_SPD_EEPROM) | |
dc9e499c | 73 | msize = spd_sdram(); |
991425fe MB |
74 | #else |
75 | msize = fixed_sdram(); | |
76 | #endif | |
77 | /* | |
78 | * Initialize SDRAM if it is on local bus. | |
79 | */ | |
80 | sdram_init(); | |
81 | ||
82 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
83 | /* | |
84 | * Initialize and enable DDR ECC. | |
85 | */ | |
86 | ddr_enable_ecc(msize * 1024 * 1024); | |
87 | #endif | |
bbea46f7 | 88 | |
991425fe MB |
89 | /* return total bus SDRAM size(bytes) -- DDR */ |
90 | return (msize * 1024 * 1024); | |
91 | } | |
92 | ||
93 | #if !defined(CONFIG_SPD_EEPROM) | |
94 | /************************************************************************* | |
95 | * fixed sdram init -- doesn't use serial presence detect. | |
96 | ************************************************************************/ | |
97 | int fixed_sdram(void) | |
98 | { | |
d239d74b | 99 | volatile immap_t *im = (immap_t *)CFG_IMMR; |
991425fe MB |
100 | u32 msize = 0; |
101 | u32 ddr_size; | |
102 | u32 ddr_size_log2; | |
103 | ||
104 | msize = CFG_DDR_SIZE; | |
105 | for (ddr_size = msize << 20, ddr_size_log2 = 0; | |
106 | (ddr_size > 1); | |
107 | ddr_size = ddr_size>>1, ddr_size_log2++) { | |
108 | if (ddr_size & 1) { | |
109 | return -1; | |
110 | } | |
111 | } | |
dc9e499c | 112 | im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); |
991425fe | 113 | im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
dc9e499c | 114 | |
991425fe MB |
115 | #if (CFG_DDR_SIZE != 256) |
116 | #warning Currenly any ddr size other than 256 is not supported | |
117 | #endif | |
d61853cf XX |
118 | #ifdef CONFIG_DDR_II |
119 | im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; | |
120 | im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; | |
121 | im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; | |
122 | im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; | |
123 | im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; | |
124 | im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; | |
125 | im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; | |
126 | im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; | |
127 | im->ddr.sdram_mode = CFG_DDR_MODE; | |
128 | im->ddr.sdram_mode2 = CFG_DDR_MODE2; | |
129 | im->ddr.sdram_interval = CFG_DDR_INTERVAL; | |
130 | im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; | |
131 | #else | |
dc9e499c | 132 | im->ddr.csbnds[2].csbnds = 0x0000000f; |
991425fe | 133 | im->ddr.cs_config[2] = CFG_DDR_CONFIG; |
dc9e499c | 134 | |
cf48eb9a | 135 | /* currently we use only one CS, so disable the other banks */ |
dc9e499c RJ |
136 | im->ddr.cs_config[0] = 0; |
137 | im->ddr.cs_config[1] = 0; | |
138 | im->ddr.cs_config[3] = 0; | |
139 | ||
140 | im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; | |
141 | im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; | |
cf48eb9a | 142 | |
991425fe MB |
143 | im->ddr.sdram_cfg = |
144 | SDRAM_CFG_SREN | |
145 | #if defined(CONFIG_DDR_2T_TIMING) | |
146 | | SDRAM_CFG_2T_EN | |
147 | #endif | |
148 | | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; | |
dc9e499c RJ |
149 | #if defined (CONFIG_DDR_32BIT) |
150 | /* for 32-bit mode burst length is 8 */ | |
151 | im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); | |
152 | #endif | |
153 | im->ddr.sdram_mode = CFG_DDR_MODE; | |
991425fe | 154 | |
cf48eb9a | 155 | im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
d61853cf | 156 | #endif |
991425fe MB |
157 | udelay(200); |
158 | ||
dc9e499c | 159 | /* enable DDR controller */ |
991425fe | 160 | im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
991425fe MB |
161 | return msize; |
162 | } | |
163 | #endif/*!CFG_SPD_EEPROM*/ | |
164 | ||
165 | ||
166 | int checkboard (void) | |
167 | { | |
168 | puts("Board: Freescale MPC8349EMDS\n"); | |
169 | return 0; | |
170 | } | |
171 | ||
991425fe MB |
172 | /* |
173 | * if MPC8349EMDS is soldered with SDRAM | |
174 | */ | |
175 | #if defined(CFG_BR2_PRELIM) \ | |
176 | && defined(CFG_OR2_PRELIM) \ | |
177 | && defined(CFG_LBLAWBAR2_PRELIM) \ | |
178 | && defined(CFG_LBLAWAR2_PRELIM) | |
179 | /* | |
180 | * Initialize SDRAM memory on the Local Bus. | |
181 | */ | |
182 | ||
183 | void sdram_init(void) | |
184 | { | |
d239d74b | 185 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
f6eda7f8 | 186 | volatile lbus83xx_t *lbc= &immap->lbus; |
991425fe MB |
187 | uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
188 | ||
991425fe MB |
189 | /* |
190 | * Setup SDRAM Base and Option Registers, already done in cpu_init.c | |
191 | */ | |
192 | ||
193 | /* setup mtrpt, lsrt and lbcr for LB bus */ | |
194 | lbc->lbcr = CFG_LBC_LBCR; | |
195 | lbc->mrtpr = CFG_LBC_MRTPR; | |
196 | lbc->lsrt = CFG_LBC_LSRT; | |
197 | asm("sync"); | |
198 | ||
199 | /* | |
200 | * Configure the SDRAM controller Machine Mode Register. | |
201 | */ | |
202 | lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ | |
203 | ||
204 | lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ | |
205 | asm("sync"); | |
206 | *sdram_addr = 0xff; | |
207 | udelay(100); | |
208 | ||
209 | lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ | |
210 | asm("sync"); | |
211 | /*1 times*/ | |
212 | *sdram_addr = 0xff; | |
213 | udelay(100); | |
214 | /*2 times*/ | |
215 | *sdram_addr = 0xff; | |
216 | udelay(100); | |
217 | /*3 times*/ | |
218 | *sdram_addr = 0xff; | |
219 | udelay(100); | |
220 | /*4 times*/ | |
221 | *sdram_addr = 0xff; | |
222 | udelay(100); | |
223 | /*5 times*/ | |
224 | *sdram_addr = 0xff; | |
225 | udelay(100); | |
226 | /*6 times*/ | |
227 | *sdram_addr = 0xff; | |
228 | udelay(100); | |
229 | /*7 times*/ | |
230 | *sdram_addr = 0xff; | |
231 | udelay(100); | |
232 | /*8 times*/ | |
233 | *sdram_addr = 0xff; | |
234 | udelay(100); | |
235 | ||
236 | /* 0x58636733; mode register write operation */ | |
237 | lbc->lsdmr = CFG_LBC_LSDMR_4; | |
238 | asm("sync"); | |
239 | *sdram_addr = 0xff; | |
240 | udelay(100); | |
241 | ||
242 | lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ | |
243 | asm("sync"); | |
244 | *sdram_addr = 0xff; | |
245 | udelay(100); | |
246 | } | |
247 | #else | |
248 | void sdram_init(void) | |
249 | { | |
991425fe MB |
250 | } |
251 | #endif | |
d326f4a2 | 252 | |
80ddd226 BW |
253 | /* |
254 | * The following are used to control the SPI chip selects for the SPI command. | |
255 | */ | |
256 | #ifdef CONFIG_HARD_SPI | |
257 | ||
258 | #define SPI_CS_MASK 0x80000000 | |
259 | ||
260 | void spi_eeprom_chipsel(int cs) | |
261 | { | |
262 | volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; | |
263 | ||
2956acd5 | 264 | if (cs) |
80ddd226 BW |
265 | iopd->dat &= ~SPI_CS_MASK; |
266 | else | |
267 | iopd->dat |= SPI_CS_MASK; | |
268 | } | |
269 | ||
270 | /* | |
271 | * The SPI command uses this table of functions for controlling the SPI | |
272 | * chip selects. | |
273 | */ | |
274 | spi_chipsel_type spi_chipsel[] = { | |
275 | spi_eeprom_chipsel, | |
276 | }; | |
277 | int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); | |
278 | ||
279 | #endif /* CONFIG_HARD_SPI */ | |
280 | ||
3fde9e8b KP |
281 | #if defined(CONFIG_OF_BOARD_SETUP) |
282 | void ft_board_setup(void *blob, bd_t *bd) | |
bf0b542d | 283 | { |
3fde9e8b KP |
284 | ft_cpu_setup(blob, bd); |
285 | #ifdef CONFIG_PCI | |
286 | ft_pci_setup(blob, bd); | |
287 | #endif | |
bf0b542d KP |
288 | } |
289 | #endif |