[people/ms/u-boot.git] / board / freescale / mpc8349emds / mpc8349emds.c

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
#include <spd.h>
#include <miiphy.h>
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

int fixed_sdram(void);
void sdram_init(void);

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
void ddr_enable_ecc(unsigned int dram_size);
#endif

int board_early_init_f (void)
{
	volatile u8* bcsr = (volatile u8*)CFG_BCSR;

	/* Enable flash write */
	bcsr[1] &= ~0x01;

#ifdef CFG_USE_MPC834XSYS_USB_PHY
	/* Use USB PHY on SYS board */
	bcsr[5] |= 0x02;
#endif

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

long int initdram (int board_type)
{
	volatile immap_t *im = (immap_t *)CFG_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CFG_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CFG_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1);
	     ddr_size = ddr_size>>1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);

#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
	im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CFG_DDR_MODE;
	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
#else
	im->ddr.csbnds[2].csbnds = 0x0000000f;
	im->ddr.cs_config[2] = CFG_DDR_CONFIG;

	/* currently we use only one CS, so disable the other banks */
	im->ddr.cs_config[0] = 0;
	im->ddr.cs_config[1] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;

	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
#if defined (CONFIG_DDR_32BIT)
	/* for 32-bit mode burst length is 8 */
	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
	im->ddr.sdram_mode = CFG_DDR_MODE;

	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
#endif
	udelay(200);

	/* enable DDR controller */
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	return msize;
}
#endif/*!CFG_SPD_EEPROM*/


int checkboard (void)
{
	puts("Board: Freescale MPC8349EMDS\n");
	return 0;
}

/*
 * if MPC8349EMDS is soldered with SDRAM
 */
#if defined(CFG_BR2_PRELIM)  \
	&& defined(CFG_OR2_PRELIM) \
	&& defined(CFG_LBLAWBAR2_PRELIM) \
	&& defined(CFG_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile lbus83xx_t *lbc= &immap->lbus;
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/* setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CFG_LBC_LBCR;
	lbc->mrtpr = CFG_LBC_MRTPR;
	lbc->lsrt = CFG_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */

	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733; mode register write operation */
	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
}
#endif

/*
 * The following are used to control the SPI chip selects for the SPI command.
 */
#ifdef CONFIG_HARD_SPI

#define SPI_CS_MASK	0x80000000

void spi_eeprom_chipsel(int cs)
{
	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];

	if(cs)
		iopd->dat &= ~SPI_CS_MASK;
	else
		iopd->dat |=  SPI_CS_MASK;
}

/*
 * The SPI command uses this table of functions for controlling the SPI
 * chip selects.
 */
spi_chipsel_type spi_chipsel[] = {
	spi_eeprom_chipsel,
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);

#endif /* CONFIG_HARD_SPI */

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
}
#endif
Commit	Line	Data
991425fe MB	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#include <common.h>
	26	#include <ioports.h>
	27	#include <mpc83xx.h>
	28	#include <asm/mpc8349_pci.h>
	29	#include <i2c.h>
80ddd226	30	#include <spi.h>
991425fe MB	31	#include <spd.h>
991425fe MB	32	#include <miiphy.h>
991425fe MB	33	#if defined(CONFIG_SPD_EEPROM)
	34	#include <spd_sdram.h>
	35	#endif
b3458d2c	36	#if defined(CONFIG_OF_LIBFDT)
3fde9e8b	37	#include <libfdt.h>
bf0b542d KP	38	#endif
bf0b542d KP	39
991425fe MB	40	int fixed_sdram(void);
	41	void sdram_init(void);
	42
	43	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
	44	void ddr_enable_ecc(unsigned int dram_size);
	45	#endif
	46
	47	int board_early_init_f (void)
	48	{
	49	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
	50
	51	/* Enable flash write */
	52	bcsr[1] &= ~0x01;
	53
8fe9bf61 KG	54	#ifdef CFG_USE_MPC834XSYS_USB_PHY
	55	/* Use USB PHY on SYS board */
	56	bcsr[5] \|= 0x02;
	57	#endif
	58
991425fe MB	59	return 0;
	60	}
	61
	62	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	63
	64	long int initdram (int board_type)
	65	{
d239d74b	66	volatile immap_t im = (immap_t )CFG_IMMR;
991425fe MB	67	u32 msize = 0;
	68
	69	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
	70	return -1;
	71
	72	/* DDR SDRAM - Main SODIMM */
	73	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
	74	#if defined(CONFIG_SPD_EEPROM)
dc9e499c	75	msize = spd_sdram();
991425fe MB	76	#else
	77	msize = fixed_sdram();
	78	#endif
	79	/*
	80	* Initialize SDRAM if it is on local bus.
	81	*/
	82	sdram_init();
	83
	84	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	85	/*
	86	* Initialize and enable DDR ECC.
	87	*/
	88	ddr_enable_ecc(msize * 1024 * 1024);
	89	#endif
bbea46f7	90
991425fe MB	91	/* return total bus SDRAM size(bytes) -- DDR */
	92	return (msize * 1024 * 1024);
	93	}
	94
	95	#if !defined(CONFIG_SPD_EEPROM)
	96	/*************************************************************************
	97	* fixed sdram init -- doesn't use serial presence detect.
	98	************************************************************************/
	99	int fixed_sdram(void)
	100	{
d239d74b	101	volatile immap_t im = (immap_t )CFG_IMMR;
991425fe MB	102	u32 msize = 0;
	103	u32 ddr_size;
	104	u32 ddr_size_log2;
	105
	106	msize = CFG_DDR_SIZE;
	107	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	108	(ddr_size > 1);
	109	ddr_size = ddr_size>>1, ddr_size_log2++) {
	110	if (ddr_size & 1) {
	111	return -1;
	112	}
	113	}
dc9e499c	114	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
991425fe	115	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
dc9e499c	116
991425fe MB	117	#if (CFG_DDR_SIZE != 256)
	118	#warning Currenly any ddr size other than 256 is not supported
	119	#endif
d61853cf XX	120	#ifdef CONFIG_DDR_II
	121	im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
	122	im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
	123	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
	124	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	125	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
	126	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
	127	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
	128	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
	129	im->ddr.sdram_mode = CFG_DDR_MODE;
	130	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
	131	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
	132	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
	133	#else
dc9e499c	134	im->ddr.csbnds[2].csbnds = 0x0000000f;
991425fe	135	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
dc9e499c	136
cf48eb9a	137	/* currently we use only one CS, so disable the other banks */
dc9e499c RJ	138	im->ddr.cs_config[0] = 0;
	139	im->ddr.cs_config[1] = 0;
	140	im->ddr.cs_config[3] = 0;
	141
	142	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	143	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
cf48eb9a	144
991425fe MB	145	im->ddr.sdram_cfg =
	146	SDRAM_CFG_SREN
	147	#if defined(CONFIG_DDR_2T_TIMING)
	148	\| SDRAM_CFG_2T_EN
	149	#endif
	150	\| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
dc9e499c RJ	151	#if defined (CONFIG_DDR_32BIT)
	152	/* for 32-bit mode burst length is 8 */
	153	im->ddr.sdram_cfg \|= (SDRAM_CFG_32_BE \| SDRAM_CFG_8_BE);
	154	#endif
	155	im->ddr.sdram_mode = CFG_DDR_MODE;
991425fe	156
cf48eb9a	157	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
d61853cf	158	#endif
991425fe MB	159	udelay(200);
991425fe MB	160
dc9e499c	161	/* enable DDR controller */
991425fe	162	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
991425fe MB	163	return msize;
	164	}
	165	#endif/!CFG_SPD_EEPROM/
	166
	167
	168	int checkboard (void)
	169	{
	170	puts("Board: Freescale MPC8349EMDS\n");
	171	return 0;
	172	}
	173
991425fe MB	174	/*
	175	* if MPC8349EMDS is soldered with SDRAM
	176	*/
	177	#if defined(CFG_BR2_PRELIM) \
	178	&& defined(CFG_OR2_PRELIM) \
	179	&& defined(CFG_LBLAWBAR2_PRELIM) \
	180	&& defined(CFG_LBLAWAR2_PRELIM)
	181	/*
	182	* Initialize SDRAM memory on the Local Bus.
	183	*/
	184
	185	void sdram_init(void)
	186	{
d239d74b	187	volatile immap_t immap = (immap_t )CFG_IMMR;
f6eda7f8	188	volatile lbus83xx_t *lbc= &immap->lbus;
991425fe MB	189	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
991425fe MB	190
991425fe MB	191	/*
	192	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	193	*/
	194
	195	/* setup mtrpt, lsrt and lbcr for LB bus */
	196	lbc->lbcr = CFG_LBC_LBCR;
	197	lbc->mrtpr = CFG_LBC_MRTPR;
	198	lbc->lsrt = CFG_LBC_LSRT;
	199	asm("sync");
	200
	201	/*
	202	* Configure the SDRAM controller Machine Mode Register.
	203	*/
	204	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
	205
	206	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	207	asm("sync");
	208	*sdram_addr = 0xff;
	209	udelay(100);
	210
	211	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	212	asm("sync");
	213	/1 times/
	214	*sdram_addr = 0xff;
	215	udelay(100);
	216	/2 times/
	217	*sdram_addr = 0xff;
	218	udelay(100);
	219	/3 times/
	220	*sdram_addr = 0xff;
	221	udelay(100);
	222	/4 times/
	223	*sdram_addr = 0xff;
	224	udelay(100);
	225	/5 times/
	226	*sdram_addr = 0xff;
	227	udelay(100);
	228	/6 times/
	229	*sdram_addr = 0xff;
	230	udelay(100);
	231	/7 times/
	232	*sdram_addr = 0xff;
	233	udelay(100);
	234	/8 times/
	235	*sdram_addr = 0xff;
	236	udelay(100);
	237
	238	/* 0x58636733; mode register write operation */
	239	lbc->lsdmr = CFG_LBC_LSDMR_4;
	240	asm("sync");
	241	*sdram_addr = 0xff;
	242	udelay(100);
	243
	244	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
	245	asm("sync");
	246	*sdram_addr = 0xff;
	247	udelay(100);
	248	}
	249	#else
	250	void sdram_init(void)
	251	{
991425fe MB	252	}
991425fe MB	253	#endif
d326f4a2	254
80ddd226 BW	255	/*
	256	* The following are used to control the SPI chip selects for the SPI command.
	257	*/
	258	#ifdef CONFIG_HARD_SPI
	259
	260	#define SPI_CS_MASK 0x80000000
	261
	262	void spi_eeprom_chipsel(int cs)
	263	{
	264	volatile gpio83xx_t iopd = &((immap_t )CFG_IMMR)->gpio[0];
	265
	266	if(cs)
	267	iopd->dat &= ~SPI_CS_MASK;
	268	else
	269	iopd->dat \|= SPI_CS_MASK;
	270	}
	271
	272	/*
	273	* The SPI command uses this table of functions for controlling the SPI
	274	* chip selects.
	275	*/
	276	spi_chipsel_type spi_chipsel[] = {
	277	spi_eeprom_chipsel,
	278	};
	279	int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
	280
	281	#endif /* CONFIG_HARD_SPI */
	282
3fde9e8b KP	283	#if defined(CONFIG_OF_BOARD_SETUP)
3fde9e8b KP	284	void ft_board_setup(void blob, bd_t bd)
bf0b542d	285	{
3fde9e8b KP	286	ft_cpu_setup(blob, bd);
	287	#ifdef CONFIG_PCI
	288	ft_pci_setup(blob, bd);
	289	#endif
bf0b542d KP	290	}
bf0b542d KP	291	#endif