[people/ms/u-boot.git] / board / freescale / mpc8360emds / mpc8360emds.c

/*
 * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <phy.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#include <spd_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <hwconfig.h>
#include <fdt_support.h>
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
#include "../../../drivers/qe/uec.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{0,  3, 1, 0, 1}, /* TxD0 */
	{0,  4, 1, 0, 1}, /* TxD1 */
	{0,  5, 1, 0, 1}, /* TxD2 */
	{0,  6, 1, 0, 1}, /* TxD3 */
	{1,  6, 1, 0, 3}, /* TxD4 */
	{1,  7, 1, 0, 1}, /* TxD5 */
	{1,  9, 1, 0, 2}, /* TxD6 */
	{1, 10, 1, 0, 2}, /* TxD7 */
	{0,  9, 2, 0, 1}, /* RxD0 */
	{0, 10, 2, 0, 1}, /* RxD1 */
	{0, 11, 2, 0, 1}, /* RxD2 */
	{0, 12, 2, 0, 1}, /* RxD3 */
	{0, 13, 2, 0, 1}, /* RxD4 */
	{1,  1, 2, 0, 2}, /* RxD5 */
	{1,  0, 2, 0, 2}, /* RxD6 */
	{1,  4, 2, 0, 2}, /* RxD7 */
	{0,  7, 1, 0, 1}, /* TX_EN */
	{0,  8, 1, 0, 1}, /* TX_ER */
	{0, 15, 2, 0, 1}, /* RX_DV */
	{0, 16, 2, 0, 1}, /* RX_ER */
	{0,  0, 2, 0, 1}, /* RX_CLK */
	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
	/* GETH2 */
	{0, 17, 1, 0, 1}, /* TxD0 */
	{0, 18, 1, 0, 1}, /* TxD1 */
	{0, 19, 1, 0, 1}, /* TxD2 */
	{0, 20, 1, 0, 1}, /* TxD3 */
	{1,  2, 1, 0, 1}, /* TxD4 */
	{1,  3, 1, 0, 2}, /* TxD5 */
	{1,  5, 1, 0, 3}, /* TxD6 */
	{1,  8, 1, 0, 3}, /* TxD7 */
	{0, 23, 2, 0, 1}, /* RxD0 */
	{0, 24, 2, 0, 1}, /* RxD1 */
	{0, 25, 2, 0, 1}, /* RxD2 */
	{0, 26, 2, 0, 1}, /* RxD3 */
	{0, 27, 2, 0, 1}, /* RxD4 */
	{1, 12, 2, 0, 2}, /* RxD5 */
	{1, 13, 2, 0, 3}, /* RxD6 */
	{1, 11, 2, 0, 2}, /* RxD7 */
	{0, 21, 1, 0, 1}, /* TX_EN */
	{0, 22, 1, 0, 1}, /* TX_ER */
	{0, 29, 2, 0, 1}, /* RX_DV */
	{0, 30, 2, 0, 1}, /* RX_ER */
	{0, 31, 2, 0, 1}, /* RX_CLK */
	{2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */

	{0,  1, 3, 0, 2}, /* MDIO */
	{0,  2, 1, 0, 1}, /* MDC */

	{5,  0, 1, 0, 2}, /* UART2_SOUT */
	{5,  1, 2, 0, 3}, /* UART2_CTS */
	{5,  2, 1, 0, 1}, /* UART2_RTS */
	{5,  3, 2, 0, 2}, /* UART2_SIN */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
static int board_handle_erratum2(void)
{
	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
	       REVID_MINOR(immr->sysconf.spridr) == 1;
}

int board_early_init_f(void)
{
	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;

	/* Enable flash write */
	bcsr[0xa] &= ~0x04;

	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
		bcsr[0xe] = 0x30;

	/* Enable second UART */
	bcsr[0x9] &= ~0x01;

	if (board_handle_erratum2()) {
		void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);

		/*
		 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
		 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
		 */
		setbits_be32(immap, 0x0c003000);

		/*
		 * IMMR + 0x14AC[20:27] = 10101010
		 * (data delay for both UCC's)
		 */
		clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
	}
	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
	pib_init();
#endif
	return 0;
}

#ifdef CONFIG_UEC_ETH
static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
	STD_UEC_INFO(1),
#endif
#ifdef CONFIG_UEC_ETH2
	STD_UEC_INFO(2),
#endif
};

int board_eth_init(bd_t *bd)
{
	if (board_handle_erratum2()) {
		int i;

		for (i = 0; i < ARRAY_SIZE(uec_info); i++)
			uec_info[i].enet_interface_type =
				PHY_INTERFACE_MODE_RGMII_RXID;
			uec_info[i].speed = SPEED_1000;
	}
	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
}
#endif /* CONFIG_UEC_ETH */

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
static int sdram_init(unsigned int base);

phys_size_t initdram(int board_type)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;
	u32 lbc_sdram_size;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize DDR ECC byte
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
	if (!msize)
		msize = lbc_sdram_size;

	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE;
	u32 ddr_size = msize << 20;
	u32 ddr_size_log2 = __ilog2(ddr_size);
	u32 half_ddr_size = ddr_size >> 1;

	im->sysconf.ddrlaw[0].bar =
		CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar =
		LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#ifdef CONFIG_DDR_II
	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else

#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
	im->ddr.csbnds[0].csbnds =
		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);
	im->ddr.csbnds[1].csbnds =
		(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
				CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);

	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;

	im->ddr.cs_config[2] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;

	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#endif
	udelay(200);
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;

	return msize;
}
#endif				/*!CONFIG_SYS_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC8360EMDS\n");
	return 0;
}

/*
 * if MPC8360EMDS is soldered with SDRAM
 */
#ifdef CONFIG_SYS_LB_SDRAM
/*
 * Initialize SDRAM memory on the Local Bus.
 */

static int sdram_init(unsigned int base)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	fsl_lbc_t *lbc = LBC_BASE_ADDR;
	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	int rem = base % sdram_size;
	uint *sdram_addr;

	/* window base address should be aligned to the window size */
	if (rem)
		base = base - rem + sdram_size;

	sdram_addr = (uint *)base;
	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_br(2, base | CONFIG_SYS_BR2);
	set_lbc_or(2, CONFIG_SYS_OR2);
	immap->sysconf.lblaw[2].bar = base;
	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

	/*setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;	/* Normal Operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;	/* Precharge All Banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * We need do 8 times auto refresh operation.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;	/* 1 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 2 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 3 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 4 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 5 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 6 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 7 times */
	udelay(100);
	*sdram_addr = 0xff;	/* 8 times */
	udelay(100);

	/* Mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*(sdram_addr + 0xcc) = 0xff;
	udelay(100);

	/* Normal operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	/*
	 * In non-aligned case we don't [normally] use that memory because
	 * there is a hole.
	 */
	if (rem)
		return 0;
	return CONFIG_SYS_LBC_SDRAM_SIZE;
}
#else
static int sdram_init(unsigned int base) { return 0; }
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
{
	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
		return;

	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
			   "peripheral", sizeof("peripheral"), 1);
}

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	ft_board_fixup_qe_usb(blob, bd);
	/*
	 * mpc8360ea pb mds errata 2: RGMII timing
	 * if on mpc8360ea rev. 2.1,
	 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	 */
	if (board_handle_erratum2()) {
		int nodeoffset;
		const char *prop;
		int path;

		nodeoffset = fdt_path_offset(blob, "/aliases");
		if (nodeoffset >= 0) {
#if defined(CONFIG_HAS_ETH0)
			/* fixup UCC 1 if using rgmii-id mode */
			prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
			if (prop) {
				path = fdt_path_offset(blob, prop);
				prop = fdt_getprop(blob, path,
				                   "phy-connection-type", 0);
				if (prop && (strcmp(prop, "rgmii-id") == 0))
					fdt_fixup_phy_connection(blob, path,
						PHY_INTERFACE_MODE_RGMII_RXID);
			}
#endif
#if defined(CONFIG_HAS_ETH1)
			/* fixup UCC 2 if using rgmii-id mode */
			prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
			if (prop) {
				path = fdt_path_offset(blob, prop);
				prop = fdt_getprop(blob, path,
				                   "phy-connection-type", 0);
				if (prop && (strcmp(prop, "rgmii-id") == 0))
					fdt_fixup_phy_connection(blob, path,
						PHY_INTERFACE_MODE_RGMII_RXID);
			}
#endif
		}
	}
}
#endif
Commit	Line	Data
5f820439	1	/*
a1964ea5	2	* Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
5f820439	3	* Dave Liu <daveliu@freescale.com>
5f820439 DL	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*/
	13
	14	#include <common.h>
	15	#include <ioports.h>
	16	#include <mpc83xx.h>
	17	#include <i2c.h>
5f820439	18	#include <miiphy.h>
865ff856	19	#include <phy.h>
5f820439 DL	20	#if defined(CONFIG_PCI)
	21	#include <pci.h>
	22	#endif
5f820439	23	#include <spd_sdram.h>
5f820439	24	#include <asm/mmu.h>
89da44ce	25	#include <asm/io.h>
a1964ea5	26	#include <asm/fsl_enet.h>
b3458d2c	27	#if defined(CONFIG_OF_LIBFDT)
213bf8c8	28	#include <libfdt.h>
213bf8c8	29	#endif
da6eea0f AV	30	#include <hwconfig.h>
da6eea0f AV	31	#include <fdt_support.h>
14778585	32	#if defined(CONFIG_PQ_MDS_PIB)
e58fe957	33	#include "../common/pq-mds-pib.h"
14778585	34	#endif
89da44ce	35	#include "../../../drivers/qe/uec.h"
5f820439	36
7737d5c6 DL	37	const qe_iop_conf_t qe_iop_conf_tab[] = {
	38	/* GETH1 */
	39	{0, 3, 1, 0, 1}, /* TxD0 */
	40	{0, 4, 1, 0, 1}, /* TxD1 */
	41	{0, 5, 1, 0, 1}, /* TxD2 */
	42	{0, 6, 1, 0, 1}, /* TxD3 */
	43	{1, 6, 1, 0, 3}, /* TxD4 */
	44	{1, 7, 1, 0, 1}, /* TxD5 */
	45	{1, 9, 1, 0, 2}, /* TxD6 */
	46	{1, 10, 1, 0, 2}, /* TxD7 */
	47	{0, 9, 2, 0, 1}, /* RxD0 */
	48	{0, 10, 2, 0, 1}, /* RxD1 */
	49	{0, 11, 2, 0, 1}, /* RxD2 */
	50	{0, 12, 2, 0, 1}, /* RxD3 */
	51	{0, 13, 2, 0, 1}, /* RxD4 */
	52	{1, 1, 2, 0, 2}, /* RxD5 */
	53	{1, 0, 2, 0, 2}, /* RxD6 */
	54	{1, 4, 2, 0, 2}, /* RxD7 */
	55	{0, 7, 1, 0, 1}, /* TX_EN */
	56	{0, 8, 1, 0, 1}, /* TX_ER */
	57	{0, 15, 2, 0, 1}, /* RX_DV */
	58	{0, 16, 2, 0, 1}, /* RX_ER */
	59	{0, 0, 2, 0, 1}, /* RX_CLK */
	60	{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
	61	{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
	62	/* GETH2 */
	63	{0, 17, 1, 0, 1}, /* TxD0 */
	64	{0, 18, 1, 0, 1}, /* TxD1 */
	65	{0, 19, 1, 0, 1}, /* TxD2 */
	66	{0, 20, 1, 0, 1}, /* TxD3 */
	67	{1, 2, 1, 0, 1}, /* TxD4 */
	68	{1, 3, 1, 0, 2}, /* TxD5 */
	69	{1, 5, 1, 0, 3}, /* TxD6 */
	70	{1, 8, 1, 0, 3}, /* TxD7 */
	71	{0, 23, 2, 0, 1}, /* RxD0 */
	72	{0, 24, 2, 0, 1}, /* RxD1 */
	73	{0, 25, 2, 0, 1}, /* RxD2 */
	74	{0, 26, 2, 0, 1}, /* RxD3 */
	75	{0, 27, 2, 0, 1}, /* RxD4 */
	76	{1, 12, 2, 0, 2}, /* RxD5 */
	77	{1, 13, 2, 0, 3}, /* RxD6 */
	78	{1, 11, 2, 0, 2}, /* RxD7 */
	79	{0, 21, 1, 0, 1}, /* TX_EN */
	80	{0, 22, 1, 0, 1}, /* TX_ER */
	81	{0, 29, 2, 0, 1}, /* RX_DV */
	82	{0, 30, 2, 0, 1}, /* RX_ER */
	83	{0, 31, 2, 0, 1}, /* RX_CLK */
	84	{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
	85	{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
	86
	87	{0, 1, 3, 0, 2}, /* MDIO */
	88	{0, 2, 1, 0, 1}, /* MDC */
	89
651d96f7 AV	90	{5, 0, 1, 0, 2}, /* UART2_SOUT */
	91	{5, 1, 2, 0, 3}, /* UART2_CTS */
	92	{5, 2, 1, 0, 1}, /* UART2_RTS */
	93	{5, 3, 2, 0, 2}, /* UART2_SIN */
	94
7737d5c6 DL	95	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	96	};
	97
89da44ce AV	98	/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
89da44ce AV	99	static int board_handle_erratum2(void)
5f820439	100	{
89da44ce	101	const immap_t immr = (immap_t )CONFIG_SYS_IMMR;
3fc0bd15	102
89da44ce AV	103	return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
	104	REVID_MINOR(immr->sysconf.spridr) == 1;
	105	}
	106
	107	int board_early_init_f(void)
	108	{
6d0f6bcf	109	const immap_t immr = (immap_t )CONFIG_SYS_IMMR;
89da44ce	110	u8 bcsr = (u8 )CONFIG_SYS_BCSR;
5f820439 DL	111
	112	/* Enable flash write */
	113	bcsr[0xa] &= ~0x04;
	114
e5c4ade4 KP	115	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
e5c4ade4 KP	116	if (REVID_MAJOR(immr->sysconf.spridr) == 2)
3fc0bd15 KP	117	bcsr[0xe] = 0x30;
3fc0bd15 KP	118
651d96f7 AV	119	/* Enable second UART */
	120	bcsr[0x9] &= ~0x01;
	121
89da44ce AV	122	if (board_handle_erratum2()) {
	123	void immap = (immap_t )(CONFIG_SYS_IMMR + 0x14a8);
	124
	125	/*
	126	* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
	127	* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
	128	*/
	129	setbits_be32(immap, 0x0c003000);
	130
	131	/*
	132	* IMMR + 0x14AC[20:27] = 10101010
	133	* (data delay for both UCC's)
	134	*/
	135	clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
	136	}
5f820439 DL	137	return 0;
	138	}
	139
14778585 TL	140	int board_early_init_r(void)
	141	{
	142	#ifdef CONFIG_PQ_MDS_PIB
	143	pib_init();
	144	#endif
	145	return 0;
	146	}
	147
89da44ce AV	148	#ifdef CONFIG_UEC_ETH
	149	static uec_info_t uec_info[] = {
	150	#ifdef CONFIG_UEC_ETH1
	151	STD_UEC_INFO(1),
	152	#endif
	153	#ifdef CONFIG_UEC_ETH2
	154	STD_UEC_INFO(2),
	155	#endif
	156	};
	157
	158	int board_eth_init(bd_t *bd)
	159	{
	160	if (board_handle_erratum2()) {
	161	int i;
	162
	163	for (i = 0; i < ARRAY_SIZE(uec_info); i++)
865ff856 AF	164	uec_info[i].enet_interface_type =
	165	PHY_INTERFACE_MODE_RGMII_RXID;
	166	uec_info[i].speed = SPEED_1000;
89da44ce AV	167	}
	168	return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
	169	}
	170	#endif /* CONFIG_UEC_ETH */
	171
9adda545	172	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5f820439 DL	173	extern void ddr_enable_ecc(unsigned int dram_size);
	174	#endif
	175	int fixed_sdram(void);
5c2ff323	176	static int sdram_init(unsigned int base);
5f820439	177
9973e3c6	178	phys_size_t initdram(int board_type)
5f820439	179	{
6d0f6bcf	180	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
5f820439	181	u32 msize = 0;
034477bb	182	u32 lbc_sdram_size;
5f820439 DL	183
	184	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	185	return -1;
	186
	187	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	188	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
5f820439 DL	189	#if defined(CONFIG_SPD_EEPROM)
	190	msize = spd_sdram();
	191	#else
	192	msize = fixed_sdram();
	193	#endif
	194
9adda545	195	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5f820439 DL	196	/*
	197	* Initialize DDR ECC byte
	198	*/
	199	ddr_enable_ecc(msize * 1024 * 1024);
	200	#endif
	201	/*
	202	* Initialize SDRAM if it is on local bus.
	203	*/
034477bb AV	204	lbc_sdram_size = sdram_init(msize * 1024 * 1024);
	205	if (!msize)
	206	msize = lbc_sdram_size;
bbea46f7	207
5f820439 DL	208	/* return total bus SDRAM size(bytes) -- DDR */
	209	return (msize * 1024 * 1024);
	210	}
	211
	212	#if !defined(CONFIG_SPD_EEPROM)
	213	/*************************************************************************
	214	* fixed sdram init -- doesn't use serial presence detect.
	215	************************************************************************/
	216	int fixed_sdram(void)
	217	{
6d0f6bcf	218	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
2e651b24 JH	219	u32 msize = CONFIG_SYS_DDR_SIZE;
	220	u32 ddr_size = msize << 20;
	221	u32 ddr_size_log2 = __ilog2(ddr_size);
	222	u32 half_ddr_size = ddr_size >> 1;
	223
	224	im->sysconf.ddrlaw[0].bar =
	225	CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
5f820439	226	im->sysconf.ddrlaw[0].ar =
2e651b24	227	LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
6d0f6bcf	228	#if (CONFIG_SYS_DDR_SIZE != 256)
5f820439 DL	229	#warning Currenly any ddr size other than 256 is not supported
5f820439 DL	230	#endif
d61853cf	231	#ifdef CONFIG_DDR_II
6d0f6bcf JCPV	232	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	233	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	234	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	235	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	236	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	237	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	238	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	239	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	240	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	241	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	242	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	243	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
d61853cf	244	#else
5f820439	245
2e651b24 JH	246	#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
	247	#warning Chip select bounds is only configurable in 16MB increments
	248	#endif
	249	im->ddr.csbnds[0].csbnds =
	250	((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	251	(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
	252	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	253	im->ddr.csbnds[1].csbnds =
	254	(((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
	255	CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	256	(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
	257	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	258
	259	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	260	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
	261
	262	im->ddr.cs_config[2] = 0;
	263	im->ddr.cs_config[3] = 0;
5f820439	264
6d0f6bcf JCPV	265	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	266	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	267	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
5f820439	268
6d0f6bcf JCPV	269	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
6d0f6bcf JCPV	270	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
d61853cf	271	#endif
5f820439 DL	272	udelay(200);
	273	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	274
	275	return msize;
	276	}
6d0f6bcf	277	#endif /!CONFIG_SYS_SPD_EEPROM /
5f820439 DL	278
	279	int checkboard(void)
	280	{
	281	puts("Board: Freescale MPC8360EMDS\n");
	282	return 0;
	283	}
	284
	285	/*
	286	* if MPC8360EMDS is soldered with SDRAM
	287	*/
5c2ff323	288	#ifdef CONFIG_SYS_LB_SDRAM
5f820439 DL	289	/*
	290	* Initialize SDRAM memory on the Local Bus.
	291	*/
	292
5c2ff323	293	static int sdram_init(unsigned int base)
5f820439	294	{
6d0f6bcf	295	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
f51cdaf1	296	fsl_lbc_t *lbc = LBC_BASE_ADDR;
5c2ff323 AV	297	const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	298	int rem = base % sdram_size;
	299	uint *sdram_addr;
5f820439	300
5c2ff323 AV	301	/* window base address should be aligned to the window size */
	302	if (rem)
	303	base = base - rem + sdram_size;
	304
	305	sdram_addr = (uint *)base;
5f820439	306	/*
5c2ff323	307	* Setup SDRAM Base and Option Registers
5f820439	308	*/
f51cdaf1 BB	309	set_lbc_br(2, base \| CONFIG_SYS_BR2);
f51cdaf1 BB	310	set_lbc_or(2, CONFIG_SYS_OR2);
5c2ff323 AV	311	immap->sysconf.lblaw[2].bar = base;
	312	immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
	313
5f820439	314	/setup mtrpt, lsrt and lbcr for LB bus /
6d0f6bcf JCPV	315	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	316	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	317	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
5f820439 DL	318	asm("sync");
	319
	320	/*
	321	* Configure the SDRAM controller Machine Mode Register.
	322	*/
6d0f6bcf JCPV	323	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
6d0f6bcf JCPV	324	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
5f820439 DL	325	asm("sync");
	326	*sdram_addr = 0xff;
	327	udelay(100);
	328
	329	/*
	330	* We need do 8 times auto refresh operation.
	331	*/
6d0f6bcf	332	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
5f820439 DL	333	asm("sync");
	334	sdram_addr = 0xff; / 1 times */
	335	udelay(100);
	336	sdram_addr = 0xff; / 2 times */
	337	udelay(100);
	338	sdram_addr = 0xff; / 3 times */
	339	udelay(100);
	340	sdram_addr = 0xff; / 4 times */
	341	udelay(100);
	342	sdram_addr = 0xff; / 5 times */
	343	udelay(100);
	344	sdram_addr = 0xff; / 6 times */
	345	udelay(100);
	346	sdram_addr = 0xff; / 7 times */
	347	udelay(100);
	348	sdram_addr = 0xff; / 8 times */
	349	udelay(100);
	350
	351	/* Mode register write operation */
6d0f6bcf	352	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
5f820439 DL	353	asm("sync");
	354	*(sdram_addr + 0xcc) = 0xff;
	355	udelay(100);
	356
	357	/* Normal operation */
6d0f6bcf	358	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 \| 0x40000000;
5f820439 DL	359	asm("sync");
	360	*sdram_addr = 0xff;
	361	udelay(100);
5c2ff323 AV	362
	363	/*
	364	* In non-aligned case we don't [normally] use that memory because
	365	* there is a hole.
	366	*/
	367	if (rem)
	368	return 0;
	369	return CONFIG_SYS_LBC_SDRAM_SIZE;
5f820439 DL	370	}
5f820439 DL	371	#else
5c2ff323	372	static int sdram_init(unsigned int base) { return 0; }
5f820439 DL	373	#endif
5f820439 DL	374
3fde9e8b	375	#if defined(CONFIG_OF_BOARD_SETUP)
da6eea0f AV	376	static void ft_board_fixup_qe_usb(void blob, bd_t bd)
	377	{
	378	if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
	379	return;
	380
	381	do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
	382	"peripheral", sizeof("peripheral"), 1);
	383	}
	384
3fde9e8b	385	void ft_board_setup(void blob, bd_t bd)
bf0b542d	386	{
3fde9e8b	387	ft_cpu_setup(blob, bd);
213bf8c8 GVB	388	#ifdef CONFIG_PCI
	389	ft_pci_setup(blob, bd);
	390	#endif
da6eea0f	391	ft_board_fixup_qe_usb(blob, bd);
24f86843 KP	392	/*
	393	* mpc8360ea pb mds errata 2: RGMII timing
	394	* if on mpc8360ea rev. 2.1,
	395	* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
	396	*/
89da44ce	397	if (board_handle_erratum2()) {
24f86843	398	int nodeoffset;
f602082b	399	const char *prop;
363eea9f	400	int path;
24f86843	401
f09880ea	402	nodeoffset = fdt_path_offset(blob, "/aliases");
24f86843	403	if (nodeoffset >= 0) {
5b8bc606 KP	404	#if defined(CONFIG_HAS_ETH0)
5b8bc606 KP	405	/* fixup UCC 1 if using rgmii-id mode */
363eea9f KP	406	prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
	407	if (prop) {
	408	path = fdt_path_offset(blob, prop);
f09880ea KP	409	prop = fdt_getprop(blob, path,
f09880ea KP	410	"phy-connection-type", 0);
5b8bc606	411	if (prop && (strcmp(prop, "rgmii-id") == 0))
a1964ea5	412	fdt_fixup_phy_connection(blob, path,
865ff856	413	PHY_INTERFACE_MODE_RGMII_RXID);
5b8bc606 KP	414	}
	415	#endif
	416	#if defined(CONFIG_HAS_ETH1)
	417	/* fixup UCC 2 if using rgmii-id mode */
363eea9f KP	418	prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
	419	if (prop) {
	420	path = fdt_path_offset(blob, prop);
f09880ea KP	421	prop = fdt_getprop(blob, path,
f09880ea KP	422	"phy-connection-type", 0);
5b8bc606	423	if (prop && (strcmp(prop, "rgmii-id") == 0))
a1964ea5	424	fdt_fixup_phy_connection(blob, path,
865ff856	425	PHY_INTERFACE_MODE_RGMII_RXID);
5b8bc606 KP	426	}
5b8bc606 KP	427	#endif
24f86843 KP	428	}
24f86843 KP	429	}
bf0b542d	430	}
3fde9e8b	431	#endif