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5f820439 DL |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
5f820439 | 3 | * Dave Liu <daveliu@freescale.com> |
5f820439 DL |
4 | * |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <common.h> | |
15 | #include <ioports.h> | |
16 | #include <mpc83xx.h> | |
17 | #include <i2c.h> | |
5f820439 | 18 | #include <miiphy.h> |
5f820439 DL |
19 | #if defined(CONFIG_PCI) |
20 | #include <pci.h> | |
21 | #endif | |
5f820439 | 22 | #include <spd_sdram.h> |
5f820439 | 23 | #include <asm/mmu.h> |
b3458d2c | 24 | #if defined(CONFIG_OF_LIBFDT) |
213bf8c8 | 25 | #include <libfdt.h> |
213bf8c8 | 26 | #endif |
14778585 | 27 | #if defined(CONFIG_PQ_MDS_PIB) |
e58fe957 | 28 | #include "../common/pq-mds-pib.h" |
14778585 | 29 | #endif |
5f820439 | 30 | |
7737d5c6 DL |
31 | const qe_iop_conf_t qe_iop_conf_tab[] = { |
32 | /* GETH1 */ | |
33 | {0, 3, 1, 0, 1}, /* TxD0 */ | |
34 | {0, 4, 1, 0, 1}, /* TxD1 */ | |
35 | {0, 5, 1, 0, 1}, /* TxD2 */ | |
36 | {0, 6, 1, 0, 1}, /* TxD3 */ | |
37 | {1, 6, 1, 0, 3}, /* TxD4 */ | |
38 | {1, 7, 1, 0, 1}, /* TxD5 */ | |
39 | {1, 9, 1, 0, 2}, /* TxD6 */ | |
40 | {1, 10, 1, 0, 2}, /* TxD7 */ | |
41 | {0, 9, 2, 0, 1}, /* RxD0 */ | |
42 | {0, 10, 2, 0, 1}, /* RxD1 */ | |
43 | {0, 11, 2, 0, 1}, /* RxD2 */ | |
44 | {0, 12, 2, 0, 1}, /* RxD3 */ | |
45 | {0, 13, 2, 0, 1}, /* RxD4 */ | |
46 | {1, 1, 2, 0, 2}, /* RxD5 */ | |
47 | {1, 0, 2, 0, 2}, /* RxD6 */ | |
48 | {1, 4, 2, 0, 2}, /* RxD7 */ | |
49 | {0, 7, 1, 0, 1}, /* TX_EN */ | |
50 | {0, 8, 1, 0, 1}, /* TX_ER */ | |
51 | {0, 15, 2, 0, 1}, /* RX_DV */ | |
52 | {0, 16, 2, 0, 1}, /* RX_ER */ | |
53 | {0, 0, 2, 0, 1}, /* RX_CLK */ | |
54 | {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ | |
55 | {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ | |
56 | /* GETH2 */ | |
57 | {0, 17, 1, 0, 1}, /* TxD0 */ | |
58 | {0, 18, 1, 0, 1}, /* TxD1 */ | |
59 | {0, 19, 1, 0, 1}, /* TxD2 */ | |
60 | {0, 20, 1, 0, 1}, /* TxD3 */ | |
61 | {1, 2, 1, 0, 1}, /* TxD4 */ | |
62 | {1, 3, 1, 0, 2}, /* TxD5 */ | |
63 | {1, 5, 1, 0, 3}, /* TxD6 */ | |
64 | {1, 8, 1, 0, 3}, /* TxD7 */ | |
65 | {0, 23, 2, 0, 1}, /* RxD0 */ | |
66 | {0, 24, 2, 0, 1}, /* RxD1 */ | |
67 | {0, 25, 2, 0, 1}, /* RxD2 */ | |
68 | {0, 26, 2, 0, 1}, /* RxD3 */ | |
69 | {0, 27, 2, 0, 1}, /* RxD4 */ | |
70 | {1, 12, 2, 0, 2}, /* RxD5 */ | |
71 | {1, 13, 2, 0, 3}, /* RxD6 */ | |
72 | {1, 11, 2, 0, 2}, /* RxD7 */ | |
73 | {0, 21, 1, 0, 1}, /* TX_EN */ | |
74 | {0, 22, 1, 0, 1}, /* TX_ER */ | |
75 | {0, 29, 2, 0, 1}, /* RX_DV */ | |
76 | {0, 30, 2, 0, 1}, /* RX_ER */ | |
77 | {0, 31, 2, 0, 1}, /* RX_CLK */ | |
78 | {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ | |
79 | {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ | |
80 | ||
81 | {0, 1, 3, 0, 2}, /* MDIO */ | |
82 | {0, 2, 1, 0, 1}, /* MDC */ | |
83 | ||
651d96f7 AV |
84 | {5, 0, 1, 0, 2}, /* UART2_SOUT */ |
85 | {5, 1, 2, 0, 3}, /* UART2_CTS */ | |
86 | {5, 2, 1, 0, 1}, /* UART2_RTS */ | |
87 | {5, 3, 2, 0, 2}, /* UART2_SIN */ | |
88 | ||
7737d5c6 DL |
89 | {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ |
90 | }; | |
91 | ||
5f820439 DL |
92 | int board_early_init_f(void) |
93 | { | |
3fc0bd15 | 94 | |
6d0f6bcf JCPV |
95 | u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; |
96 | const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; | |
5f820439 DL |
97 | |
98 | /* Enable flash write */ | |
99 | bcsr[0xa] &= ~0x04; | |
100 | ||
e5c4ade4 KP |
101 | /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */ |
102 | if (REVID_MAJOR(immr->sysconf.spridr) == 2) | |
3fc0bd15 KP |
103 | bcsr[0xe] = 0x30; |
104 | ||
651d96f7 AV |
105 | /* Enable second UART */ |
106 | bcsr[0x9] &= ~0x01; | |
107 | ||
5f820439 DL |
108 | return 0; |
109 | } | |
110 | ||
14778585 TL |
111 | int board_early_init_r(void) |
112 | { | |
113 | #ifdef CONFIG_PQ_MDS_PIB | |
114 | pib_init(); | |
115 | #endif | |
116 | return 0; | |
117 | } | |
118 | ||
5f820439 DL |
119 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) |
120 | extern void ddr_enable_ecc(unsigned int dram_size); | |
121 | #endif | |
122 | int fixed_sdram(void); | |
123 | void sdram_init(void); | |
124 | ||
9973e3c6 | 125 | phys_size_t initdram(int board_type) |
5f820439 | 126 | { |
6d0f6bcf | 127 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
5f820439 DL |
128 | u32 msize = 0; |
129 | ||
130 | if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) | |
131 | return -1; | |
132 | ||
133 | /* DDR SDRAM - Main SODIMM */ | |
6d0f6bcf | 134 | im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
5f820439 DL |
135 | #if defined(CONFIG_SPD_EEPROM) |
136 | msize = spd_sdram(); | |
137 | #else | |
138 | msize = fixed_sdram(); | |
139 | #endif | |
140 | ||
141 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) | |
142 | /* | |
143 | * Initialize DDR ECC byte | |
144 | */ | |
145 | ddr_enable_ecc(msize * 1024 * 1024); | |
146 | #endif | |
147 | /* | |
148 | * Initialize SDRAM if it is on local bus. | |
149 | */ | |
150 | sdram_init(); | |
bbea46f7 | 151 | |
5f820439 DL |
152 | /* return total bus SDRAM size(bytes) -- DDR */ |
153 | return (msize * 1024 * 1024); | |
154 | } | |
155 | ||
156 | #if !defined(CONFIG_SPD_EEPROM) | |
157 | /************************************************************************* | |
158 | * fixed sdram init -- doesn't use serial presence detect. | |
159 | ************************************************************************/ | |
160 | int fixed_sdram(void) | |
161 | { | |
6d0f6bcf | 162 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
5f820439 DL |
163 | u32 msize = 0; |
164 | u32 ddr_size; | |
165 | u32 ddr_size_log2; | |
166 | ||
6d0f6bcf | 167 | msize = CONFIG_SYS_DDR_SIZE; |
5f820439 DL |
168 | for (ddr_size = msize << 20, ddr_size_log2 = 0; |
169 | (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { | |
170 | if (ddr_size & 1) { | |
171 | return -1; | |
172 | } | |
173 | } | |
174 | im->sysconf.ddrlaw[0].ar = | |
175 | LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); | |
6d0f6bcf | 176 | #if (CONFIG_SYS_DDR_SIZE != 256) |
5f820439 DL |
177 | #warning Currenly any ddr size other than 256 is not supported |
178 | #endif | |
d61853cf | 179 | #ifdef CONFIG_DDR_II |
6d0f6bcf JCPV |
180 | im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; |
181 | im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; | |
182 | im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; | |
183 | im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; | |
184 | im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; | |
185 | im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; | |
186 | im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; | |
187 | im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; | |
188 | im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; | |
189 | im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; | |
190 | im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; | |
191 | im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; | |
d61853cf | 192 | #else |
5f820439 DL |
193 | im->ddr.csbnds[0].csbnds = 0x00000007; |
194 | im->ddr.csbnds[1].csbnds = 0x0008000f; | |
195 | ||
6d0f6bcf JCPV |
196 | im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; |
197 | im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG; | |
5f820439 | 198 | |
6d0f6bcf JCPV |
199 | im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
200 | im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; | |
201 | im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; | |
5f820439 | 202 | |
6d0f6bcf JCPV |
203 | im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
204 | im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; | |
d61853cf | 205 | #endif |
5f820439 DL |
206 | udelay(200); |
207 | im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; | |
208 | ||
209 | return msize; | |
210 | } | |
6d0f6bcf | 211 | #endif /*!CONFIG_SYS_SPD_EEPROM */ |
5f820439 DL |
212 | |
213 | int checkboard(void) | |
214 | { | |
215 | puts("Board: Freescale MPC8360EMDS\n"); | |
216 | return 0; | |
217 | } | |
218 | ||
219 | /* | |
220 | * if MPC8360EMDS is soldered with SDRAM | |
221 | */ | |
6d0f6bcf JCPV |
222 | #if defined(CONFIG_SYS_BR2_PRELIM) \ |
223 | && defined(CONFIG_SYS_OR2_PRELIM) \ | |
224 | && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ | |
225 | && defined(CONFIG_SYS_LBLAWAR2_PRELIM) | |
5f820439 DL |
226 | /* |
227 | * Initialize SDRAM memory on the Local Bus. | |
228 | */ | |
229 | ||
230 | void sdram_init(void) | |
231 | { | |
6d0f6bcf | 232 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
5f820439 | 233 | volatile lbus83xx_t *lbc = &immap->lbus; |
6d0f6bcf | 234 | uint *sdram_addr = (uint *) CONFIG_SYS_LBC_SDRAM_BASE; |
5f820439 | 235 | |
5f820439 DL |
236 | /* |
237 | * Setup SDRAM Base and Option Registers, already done in cpu_init.c | |
238 | */ | |
239 | /*setup mtrpt, lsrt and lbcr for LB bus */ | |
6d0f6bcf JCPV |
240 | lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
241 | lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; | |
242 | lbc->lsrt = CONFIG_SYS_LBC_LSRT; | |
5f820439 DL |
243 | asm("sync"); |
244 | ||
245 | /* | |
246 | * Configure the SDRAM controller Machine Mode Register. | |
247 | */ | |
6d0f6bcf JCPV |
248 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ |
249 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ | |
5f820439 DL |
250 | asm("sync"); |
251 | *sdram_addr = 0xff; | |
252 | udelay(100); | |
253 | ||
254 | /* | |
255 | * We need do 8 times auto refresh operation. | |
256 | */ | |
6d0f6bcf | 257 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; |
5f820439 DL |
258 | asm("sync"); |
259 | *sdram_addr = 0xff; /* 1 times */ | |
260 | udelay(100); | |
261 | *sdram_addr = 0xff; /* 2 times */ | |
262 | udelay(100); | |
263 | *sdram_addr = 0xff; /* 3 times */ | |
264 | udelay(100); | |
265 | *sdram_addr = 0xff; /* 4 times */ | |
266 | udelay(100); | |
267 | *sdram_addr = 0xff; /* 5 times */ | |
268 | udelay(100); | |
269 | *sdram_addr = 0xff; /* 6 times */ | |
270 | udelay(100); | |
271 | *sdram_addr = 0xff; /* 7 times */ | |
272 | udelay(100); | |
273 | *sdram_addr = 0xff; /* 8 times */ | |
274 | udelay(100); | |
275 | ||
276 | /* Mode register write operation */ | |
6d0f6bcf | 277 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; |
5f820439 DL |
278 | asm("sync"); |
279 | *(sdram_addr + 0xcc) = 0xff; | |
280 | udelay(100); | |
281 | ||
282 | /* Normal operation */ | |
6d0f6bcf | 283 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; |
5f820439 DL |
284 | asm("sync"); |
285 | *sdram_addr = 0xff; | |
286 | udelay(100); | |
287 | } | |
288 | #else | |
289 | void sdram_init(void) | |
290 | { | |
5f820439 DL |
291 | } |
292 | #endif | |
293 | ||
3fde9e8b KP |
294 | #if defined(CONFIG_OF_BOARD_SETUP) |
295 | void ft_board_setup(void *blob, bd_t *bd) | |
bf0b542d | 296 | { |
6d0f6bcf | 297 | const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
b3458d2c | 298 | |
3fde9e8b | 299 | ft_cpu_setup(blob, bd); |
213bf8c8 GVB |
300 | #ifdef CONFIG_PCI |
301 | ft_pci_setup(blob, bd); | |
302 | #endif | |
24f86843 KP |
303 | /* |
304 | * mpc8360ea pb mds errata 2: RGMII timing | |
305 | * if on mpc8360ea rev. 2.1, | |
306 | * change both ucc phy-connection-types from rgmii-id to rgmii-rxid | |
307 | */ | |
e5c4ade4 KP |
308 | if ((REVID_MAJOR(immr->sysconf.spridr) == 2) && |
309 | (REVID_MINOR(immr->sysconf.spridr) == 1)) { | |
24f86843 | 310 | int nodeoffset; |
f602082b | 311 | const char *prop; |
363eea9f | 312 | int path; |
24f86843 | 313 | |
f09880ea | 314 | nodeoffset = fdt_path_offset(blob, "/aliases"); |
24f86843 | 315 | if (nodeoffset >= 0) { |
5b8bc606 KP |
316 | #if defined(CONFIG_HAS_ETH0) |
317 | /* fixup UCC 1 if using rgmii-id mode */ | |
363eea9f KP |
318 | prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL); |
319 | if (prop) { | |
320 | path = fdt_path_offset(blob, prop); | |
f09880ea KP |
321 | prop = fdt_getprop(blob, path, |
322 | "phy-connection-type", 0); | |
5b8bc606 | 323 | if (prop && (strcmp(prop, "rgmii-id") == 0)) |
f09880ea KP |
324 | fdt_setprop(blob, path, |
325 | "phy-connection-type", | |
326 | "rgmii-rxid", | |
327 | sizeof("rgmii-rxid")); | |
5b8bc606 KP |
328 | } |
329 | #endif | |
330 | #if defined(CONFIG_HAS_ETH1) | |
331 | /* fixup UCC 2 if using rgmii-id mode */ | |
363eea9f KP |
332 | prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL); |
333 | if (prop) { | |
334 | path = fdt_path_offset(blob, prop); | |
f09880ea KP |
335 | prop = fdt_getprop(blob, path, |
336 | "phy-connection-type", 0); | |
5b8bc606 | 337 | if (prop && (strcmp(prop, "rgmii-id") == 0)) |
f09880ea KP |
338 | fdt_setprop(blob, path, |
339 | "phy-connection-type", | |
340 | "rgmii-rxid", | |
341 | sizeof("rgmii-rxid")); | |
5b8bc606 KP |
342 | } |
343 | #endif | |
24f86843 KP |
344 | } |
345 | } | |
bf0b542d | 346 | } |
3fde9e8b | 347 | #endif |