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5f820439 DL |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * PCI Configuration space access support for MPC83xx PCI Bridge | |
15 | */ | |
16 | #include <asm/mmu.h> | |
17 | #include <asm/io.h> | |
18 | #include <common.h> | |
19 | #include <pci.h> | |
20 | #include <i2c.h> | |
781e026c KP |
21 | #if defined(CONFIG_OF_FLAT_TREE) |
22 | #include <ft_build.h> | |
26d02c9b | 23 | #elif defined(CONFIG_OF_LIBFDT) |
213bf8c8 | 24 | #include <libfdt.h> |
213bf8c8 | 25 | #endif |
5f820439 | 26 | |
be5e6181 | 27 | #include <asm/fsl_i2c.h> |
5f820439 DL |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #if defined(CONFIG_PCI) | |
32 | #define PCI_FUNCTION_CONFIG 0x44 | |
33 | #define PCI_FUNCTION_CFG_LOCK 0x20 | |
34 | ||
35 | /* | |
36 | * Initialize PCI Devices, report devices found | |
37 | */ | |
38 | #ifndef CONFIG_PCI_PNP | |
39 | static struct pci_config_table pci_mpc83xxemds_config_table[] = { | |
40 | { | |
41 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
42 | pci_cfgfunc_config_device, | |
43 | {PCI_ENET0_IOADDR, | |
44 | PCI_ENET0_MEMADDR, | |
45 | PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} | |
46 | }, | |
47 | {} | |
48 | } | |
49 | #endif | |
50 | static struct pci_controller hose[] = { | |
51 | { | |
52 | #ifndef CONFIG_PCI_PNP | |
53 | config_table:pci_mpc83xxemds_config_table, | |
54 | #endif | |
55 | }, | |
56 | }; | |
57 | ||
58 | /********************************************************************** | |
59 | * pci_init_board() | |
60 | *********************************************************************/ | |
61 | void pci_init_board(void) | |
62 | #ifdef CONFIG_PCISLAVE | |
63 | { | |
64 | u16 reg16; | |
65 | volatile immap_t *immr; | |
66 | volatile law83xx_t *pci_law; | |
67 | volatile pot83xx_t *pci_pot; | |
68 | volatile pcictrl83xx_t *pci_ctrl; | |
69 | volatile pciconf83xx_t *pci_conf; | |
70 | ||
d239d74b | 71 | immr = (immap_t *) CFG_IMMR; |
5f820439 DL |
72 | pci_law = immr->sysconf.pcilaw; |
73 | pci_pot = immr->ios.pot; | |
74 | pci_ctrl = immr->pci_ctrl; | |
75 | pci_conf = immr->pci_conf; | |
76 | /* | |
77 | * Configure PCI Inbound Translation Windows | |
78 | */ | |
79 | pci_ctrl[0].pitar0 = 0x0; | |
80 | pci_ctrl[0].pibar0 = 0x0; | |
81 | pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | | |
82 | PIWAR_WTT_SNOOP | PIWAR_IWS_4K; | |
83 | ||
84 | pci_ctrl[0].pitar1 = 0x0; | |
85 | pci_ctrl[0].pibar1 = 0x0; | |
86 | pci_ctrl[0].piebar1 = 0x0; | |
87 | pci_ctrl[0].piwar1 &= ~PIWAR_EN; | |
88 | ||
89 | pci_ctrl[0].pitar2 = 0x0; | |
90 | pci_ctrl[0].pibar2 = 0x0; | |
91 | pci_ctrl[0].piebar2 = 0x0; | |
92 | pci_ctrl[0].piwar2 &= ~PIWAR_EN; | |
93 | ||
94 | hose[0].first_busno = 0; | |
95 | hose[0].last_busno = 0xff; | |
96 | pci_setup_indirect(&hose[0], | |
d239d74b | 97 | (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
5f820439 DL |
98 | reg16 = 0xff; |
99 | ||
100 | pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), | |
101 | PCI_COMMAND, ®16); | |
102 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; | |
103 | pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), | |
104 | PCI_COMMAND, reg16); | |
105 | ||
106 | /* | |
107 | * Clear non-reserved bits in status register. | |
108 | */ | |
109 | pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), | |
110 | PCI_STATUS, 0xffff); | |
111 | pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), | |
112 | PCI_LATENCY_TIMER, 0x80); | |
113 | ||
114 | /* | |
115 | * Unlock configuration lock in PCI function configuration register. | |
116 | */ | |
117 | pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), | |
118 | PCI_FUNCTION_CONFIG, ®16); | |
119 | reg16 &= ~(PCI_FUNCTION_CFG_LOCK); | |
120 | pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), | |
121 | PCI_FUNCTION_CONFIG, reg16); | |
122 | ||
123 | printf("Enabled PCI 32bit Agent Mode\n"); | |
124 | } | |
125 | #else | |
126 | { | |
127 | volatile immap_t *immr; | |
128 | volatile clk83xx_t *clk; | |
129 | volatile law83xx_t *pci_law; | |
130 | volatile pot83xx_t *pci_pot; | |
131 | volatile pcictrl83xx_t *pci_ctrl; | |
132 | volatile pciconf83xx_t *pci_conf; | |
133 | ||
5f820439 DL |
134 | u16 reg16; |
135 | u32 val32; | |
136 | u32 dev; | |
137 | ||
d239d74b | 138 | immr = (immap_t *) CFG_IMMR; |
5f820439 DL |
139 | clk = (clk83xx_t *) & immr->clk; |
140 | pci_law = immr->sysconf.pcilaw; | |
141 | pci_pot = immr->ios.pot; | |
142 | pci_ctrl = immr->pci_ctrl; | |
143 | pci_conf = immr->pci_conf; | |
144 | /* | |
145 | * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode | |
146 | */ | |
147 | val32 = clk->occr; | |
148 | udelay(2000); | |
149 | #if defined(PCI_66M) | |
150 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; | |
151 | printf("PCI clock is 66MHz\n"); | |
152 | #elif defined(PCI_33M) | |
153 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | | |
154 | OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; | |
155 | printf("PCI clock is 33MHz\n"); | |
156 | #else | |
157 | clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; | |
158 | printf("PCI clock is 66MHz\n"); | |
159 | #endif | |
160 | udelay(2000); | |
161 | ||
162 | /* | |
163 | * Configure PCI Local Access Windows | |
164 | */ | |
165 | pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; | |
166 | pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; | |
167 | ||
168 | pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; | |
169 | pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; | |
170 | ||
171 | /* | |
172 | * Configure PCI Outbound Translation Windows | |
173 | */ | |
174 | ||
175 | /* PCI mem space - prefetch */ | |
176 | pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; | |
177 | pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; | |
178 | pci_pot[0].pocmr = | |
179 | POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); | |
180 | ||
181 | /* PCI mmio - non-prefetch mem space */ | |
182 | pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; | |
183 | pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; | |
184 | pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); | |
185 | ||
186 | /* PCI IO space */ | |
187 | pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; | |
188 | pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; | |
189 | pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); | |
190 | ||
191 | /* | |
192 | * Configure PCI Inbound Translation Windows | |
193 | */ | |
194 | pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; | |
195 | pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; | |
196 | pci_ctrl[0].piebar1 = 0x0; | |
197 | pci_ctrl[0].piwar1 = | |
198 | PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | | |
199 | PIWAR_IWS_2G; | |
200 | ||
5f820439 DL |
201 | /* |
202 | * Release PCI RST Output signal | |
203 | */ | |
204 | udelay(2000); | |
205 | pci_ctrl[0].gcr = 1; | |
206 | udelay(2000); | |
207 | ||
208 | hose[0].first_busno = 0; | |
209 | hose[0].last_busno = 0xff; | |
210 | ||
211 | /* PCI memory prefetch space */ | |
212 | pci_set_region(hose[0].regions + 0, | |
213 | CFG_PCI_MEM_BASE, | |
214 | CFG_PCI_MEM_PHYS, | |
215 | CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); | |
216 | ||
217 | /* PCI memory space */ | |
218 | pci_set_region(hose[0].regions + 1, | |
219 | CFG_PCI_MMIO_BASE, | |
220 | CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); | |
221 | ||
222 | /* PCI IO space */ | |
223 | pci_set_region(hose[0].regions + 2, | |
224 | CFG_PCI_IO_BASE, | |
225 | CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); | |
226 | ||
227 | /* System memory space */ | |
228 | pci_set_region(hose[0].regions + 3, | |
229 | CFG_PCI_SLV_MEM_LOCAL, | |
230 | CFG_PCI_SLV_MEM_BUS, | |
231 | CFG_PCI_SLV_MEM_SIZE, | |
232 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
233 | ||
234 | hose[0].region_count = 4; | |
235 | ||
236 | pci_setup_indirect(&hose[0], | |
d239d74b | 237 | (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
5f820439 DL |
238 | |
239 | pci_register_hose(hose); | |
240 | ||
241 | /* | |
242 | * Write command register | |
243 | */ | |
244 | reg16 = 0xff; | |
245 | dev = PCI_BDF(0, 0, 0); | |
246 | pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); | |
247 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | |
248 | pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); | |
249 | ||
250 | /* | |
251 | * Clear non-reserved bits in status register. | |
252 | */ | |
253 | pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); | |
254 | pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); | |
255 | pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); | |
256 | ||
5f820439 DL |
257 | /* |
258 | * Hose scan. | |
259 | */ | |
260 | hose->last_busno = pci_hose_scan(hose); | |
261 | } | |
262 | #endif /* CONFIG_PCISLAVE */ | |
bf0b542d | 263 | |
213bf8c8 GVB |
264 | #if defined(CONFIG_OF_LIBFDT) |
265 | void | |
266 | ft_pci_setup(void *blob, bd_t *bd) | |
267 | { | |
268 | int nodeoffset; | |
269 | int err; | |
270 | int tmp[2]; | |
271 | ||
8d04f02f | 272 | nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500"); |
213bf8c8 GVB |
273 | if (nodeoffset >= 0) { |
274 | tmp[0] = cpu_to_be32(hose[0].first_busno); | |
275 | tmp[1] = cpu_to_be32(hose[0].last_busno); | |
8f9e0e9f KP |
276 | err = fdt_setprop(blob, nodeoffset, "bus-range", |
277 | tmp, sizeof(tmp)); | |
278 | ||
279 | tmp[0] = cpu_to_be32(gd->pci_clk); | |
280 | err = fdt_setprop(blob, nodeoffset, "clock-frequency", | |
281 | tmp, sizeof(tmp[0])); | |
213bf8c8 GVB |
282 | } |
283 | } | |
26d02c9b | 284 | #elif defined(CONFIG_OF_FLAT_TREE) |
bf0b542d KP |
285 | void |
286 | ft_pci_setup(void *blob, bd_t *bd) | |
287 | { | |
26d02c9b JVB |
288 | u32 *p; |
289 | int len; | |
bf0b542d | 290 | |
26d02c9b JVB |
291 | p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
292 | if (p != NULL) { | |
bf0b542d KP |
293 | p[0] = hose[0].first_busno; |
294 | p[1] = hose[0].last_busno; | |
26d02c9b | 295 | } |
bf0b542d KP |
296 | } |
297 | #endif /* CONFIG_OF_FLAT_TREE */ | |
5f820439 | 298 | #endif /* CONFIG_PCI */ |