[people/ms/u-boot.git] / board / freescale / mpc837xerdb / mpc837xerdb.c

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Kevin Lam <kevin.lam@freescale.com>
 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <vsc7385.h>
#include <fsl_esdhc.h>

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);

phys_size_t initdram(int board_type)
{
	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
		return -1;

#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/* Initialize DDR ECC byte */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* return total bus DDR size(bytes) */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
	u32 msize_log2 = __ilog2(msize);

	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);

	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
	udelay(50000);

	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
	udelay(1000);

	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
	udelay(1000);

	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	sync();
	udelay(1000);

	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	udelay(2000);
	return CONFIG_SYS_DDR_SIZE;
}
#endif	/*!CONFIG_SYS_SPD_EEPROM */

int checkboard(void)
{
	puts("Board: Freescale MPC837xERDB\n");
	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_FSL_SERDES
	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
	u32 spridr = in_be32(&immr->sysconf.spridr);

	/* we check only part num, and don't look for CPU revisions */
	switch (PARTID_NO_E(spridr)) {
	case SPR_8377:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	case SPR_8378:
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	case SPR_8379:
		fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
				 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
		break;
	default:
		printf("serdes not configured: unknown CPU part number: "
		       "%04x\n", spridr >> 16);
		break;
	}
#endif /* CONFIG_FSL_SERDES */
	return 0;
}

#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bd)
{
	struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
	int esdhc_hwconfig_enabled = 0;

	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
		esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);

	if (esdhc_hwconfig_enabled == 0)
		return 0;

	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
	clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);

	return fsl_esdhc_mmc_init(bd);
}
#endif

/*
 * Miscellaneous late-boot configurations
 *
 * If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
	int rc = 0;

#ifdef CONFIG_VSC7385_IMAGE
	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
		CONFIG_VSC7385_IMAGE_SIZE)) {
		puts("Failure uploading VSC7385 microcode.\n");
		rc = 1;
	}
#endif

	return rc;
}

#if defined(CONFIG_OF_BOARD_SETUP)

int ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	ft_cpu_setup(blob, bd);
	fdt_fixup_dr_usb(blob, bd);
	fdt_fixup_esdhc(blob, bd);

	return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
5e918a98 KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	* Kevin Lam <kevin.lam@freescale.com>
	4	* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
5e918a98 KP	7	*/
	8
	9	#include <common.h>
c9646ed7	10	#include <hwconfig.h>
5e918a98	11	#include <i2c.h>
5e918a98	12	#include <asm/io.h>
7e1afb62	13	#include <asm/fsl_mpc83xx_serdes.h>
1ac4f320	14	#include <fdt_support.h>
5e918a98	15	#include <spd_sdram.h>
89c7784e	16	#include <vsc7385.h>
c9646ed7	17	#include <fsl_esdhc.h>
89c7784e	18
6d0f6bcf	19	#if defined(CONFIG_SYS_DRAM_TEST)
5e918a98 KP	20	int
	21	testdram(void)
	22	{
6d0f6bcf JCPV	23	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	24	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
5e918a98 KP	25	uint *p;
	26
	27	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	28	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	29	CONFIG_SYS_MEMTEST_END);
5e918a98 KP	30
	31	printf("DRAM test phase 1:\n");
	32	for (p = pstart; p < pend; p++)
	33	*p = 0xaaaaaaaa;
	34
	35	for (p = pstart; p < pend; p++) {
	36	if (*p != 0xaaaaaaaa) {
	37	printf("DRAM test fails at: %08x\n", (uint) p);
	38	return 1;
	39	}
	40	}
	41
	42	printf("DRAM test phase 2:\n");
	43	for (p = pstart; p < pend; p++)
	44	*p = 0x55555555;
	45
	46	for (p = pstart; p < pend; p++) {
	47	if (*p != 0x55555555) {
	48	printf("DRAM test fails at: %08x\n", (uint) p);
	49	return 1;
	50	}
	51	}
	52
	53	printf("DRAM test passed.\n");
	54	return 0;
	55	}
	56	#endif
	57
9adda545	58	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5e918a98 KP	59	void ddr_enable_ecc(unsigned int dram_size);
	60	#endif
	61	int fixed_sdram(void);
	62
9973e3c6	63	phys_size_t initdram(int board_type)
5e918a98	64	{
6d0f6bcf	65	immap_t im = (immap_t ) CONFIG_SYS_IMMR;
5e918a98 KP	66	u32 msize = 0;
	67
	68	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
	69	return -1;
	70
	71	#if defined(CONFIG_SPD_EEPROM)
	72	msize = spd_sdram();
	73	#else
	74	msize = fixed_sdram();
	75	#endif
	76
9adda545	77	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
5e918a98 KP	78	/* Initialize DDR ECC byte */
	79	ddr_enable_ecc(msize * 1024 * 1024);
	80	#endif
	81	/* return total bus DDR size(bytes) */
	82	return (msize * 1024 * 1024);
	83	}
	84
	85	#if !defined(CONFIG_SPD_EEPROM)
	86	/*************************************************************************
	87	* fixed sdram init -- doesn't use serial presence detect.
	88	************************************************************************/
	89	int fixed_sdram(void)
	90	{
6d0f6bcf JCPV	91	immap_t im = (immap_t ) CONFIG_SYS_IMMR;
6d0f6bcf JCPV	92	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
5e918a98 KP	93	u32 msize_log2 = __ilog2(msize);
5e918a98 KP	94
6d0f6bcf	95	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
5e918a98 KP	96	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN \| (msize_log2 - 1);
5e918a98 KP	97
6d0f6bcf	98	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
5e918a98 KP	99	udelay(50000);
5e918a98 KP	100
6d0f6bcf	101	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
5e918a98 KP	102	udelay(1000);
5e918a98 KP	103
6d0f6bcf JCPV	104	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	105	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
5e918a98 KP	106	udelay(1000);
5e918a98 KP	107
6d0f6bcf JCPV	108	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	109	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	110	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	111	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	112	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
	113	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
	114	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
	115	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
	116	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
5e918a98 KP	117	sync();
	118	udelay(1000);
	119
	120	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	121	udelay(2000);
6d0f6bcf	122	return CONFIG_SYS_DDR_SIZE;
5e918a98	123	}
6d0f6bcf	124	#endif /!CONFIG_SYS_SPD_EEPROM /
5e918a98 KP	125
	126	int checkboard(void)
	127	{
	128	puts("Board: Freescale MPC837xERDB\n");
	129	return 0;
	130	}
	131
2bd7460e AV	132	int board_early_init_f(void)
	133	{
	134	#ifdef CONFIG_FSL_SERDES
6d0f6bcf	135	immap_t immr = (immap_t )CONFIG_SYS_IMMR;
2bd7460e AV	136	u32 spridr = in_be32(&immr->sysconf.spridr);
	137
	138	/* we check only part num, and don't look for CPU revisions */
e5c4ade4 KP	139	switch (PARTID_NO_E(spridr)) {
e5c4ade4 KP	140	case SPR_8377:
2bd7460e AV	141	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
2bd7460e AV	142	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
e5c4ade4	143	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
2bd7460e AV	144	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
2bd7460e AV	145	break;
e5c4ade4	146	case SPR_8378:
55c53198	147	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
2bd7460e AV	148	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
2bd7460e AV	149	break;
e5c4ade4	150	case SPR_8379:
2bd7460e AV	151	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
2bd7460e AV	152	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
e5c4ade4	153	fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
2bd7460e AV	154	FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
	155	break;
	156	default:
	157	printf("serdes not configured: unknown CPU part number: "
	158	"%04x\n", spridr >> 16);
	159	break;
	160	}
	161	#endif /* CONFIG_FSL_SERDES */
	162	return 0;
	163	}
	164
c9646ed7 AV	165	#ifdef CONFIG_FSL_ESDHC
	166	int board_mmc_init(bd_t *bd)
	167	{
	168	struct immap __iomem im = (struct immap __iomem )CONFIG_SYS_IMMR;
19e5118d SA	169	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
19e5118d SA	170	int esdhc_hwconfig_enabled = 0;
c9646ed7	171
19e5118d SA	172	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
	173	esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
	174
	175	if (esdhc_hwconfig_enabled == 0)
c9646ed7 AV	176	return 0;
	177
	178	clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
	179	clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
	180
	181	return fsl_esdhc_mmc_init(bd);
	182	}
	183	#endif
	184
89c7784e TT	185	/*
	186	* Miscellaneous late-boot configurations
	187	*
	188	* If a VSC7385 microcode image is present, then upload it.
	189	*/
	190	int misc_init_r(void)
	191	{
	192	int rc = 0;
	193
	194	#ifdef CONFIG_VSC7385_IMAGE
	195	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
	196	CONFIG_VSC7385_IMAGE_SIZE)) {
	197	puts("Failure uploading VSC7385 microcode.\n");
	198	rc = 1;
	199	}
	200	#endif
	201
	202	return rc;
	203	}
	204
5e918a98 KP	205	#if defined(CONFIG_OF_BOARD_SETUP)
5e918a98 KP	206
e895a4b0	207	int ft_board_setup(void blob, bd_t bd)
5e918a98 KP	208	{
	209	#ifdef CONFIG_PCI
	210	ft_pci_setup(blob, bd);
	211	#endif
	212	ft_cpu_setup(blob, bd);
18e69a35	213	fdt_fixup_dr_usb(blob, bd);
c9646ed7	214	fdt_fixup_esdhc(blob, bd);
e895a4b0 SG	215
e895a4b0 SG	216	return 0;
5e918a98 KP	217	}
5e918a98 KP	218	#endif /* CONFIG_OF_BOARD_SETUP */