[thirdparty/u-boot.git] / board / freescale / mpc837xerdb / pci.c

/*
 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <asm/io.h>

static struct pci_region pci_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI_MEM_BASE,
		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
		size: CONFIG_SYS_PCI_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
		size: CONFIG_SYS_PCI_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
	{
		bus_start: CONFIG_SYS_PCI_IO_BASE,
		phys_start: CONFIG_SYS_PCI_IO_PHYS,
		size: CONFIG_SYS_PCI_IO_SIZE,
		flags: PCI_REGION_IO
	}
};

static struct pci_region pcie_regions_0[] = {
	{
		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
		.size = CONFIG_SYS_PCIE1_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

static struct pci_region pcie_regions_1[] = {
	{
		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
		.flags = PCI_REGION_MEM,
	},
	{
		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
		.size = CONFIG_SYS_PCIE2_IO_SIZE,
		.flags = PCI_REGION_IO,
	},
};

void pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile sysconf83xx_t *sysconf = &immr->sysconf;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	volatile law83xx_t *pcie_law = sysconf->pcielaw;
	struct pci_region *reg[] = { pci_regions };
	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
	u32 spridr = in_be32(&immr->sysconf.spridr);

	/* Enable all 5 PCI_CLK_OUTPUTS */
	clk->occr |= 0xf8000000;
	udelay(2000);

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;

	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;

	mpc83xx_pci_init(1, reg);

	/* There is no PEX in MPC8379 parts. */
	if (PARTID_NO_E(spridr) == SPR_8379)
		return;

	/* Configure the clock for PCIE controller */
	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);

	/* Deassert the resets in the control register */
	out_be32(&sysconf->pecr1, 0xE0008000);
	out_be32(&sysconf->pecr2, 0xE0008000);
	udelay(2000);

	/* Configure PCI Express Local Access Windows */
	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);

	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);

	mpc83xx_pcie_init(2, pcie_reg);
}
Commit	Line	Data
5e918a98	1	/*
9993e196	2	* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5e918a98	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
5e918a98 KP	5	*/
	6
	7	#include <common.h>
	8	#include <mpc83xx.h>
	9	#include <pci.h>
7e915580	10	#include <asm/io.h>
5e918a98	11
5e918a98 KP	12	static struct pci_region pci_regions[] = {
5e918a98 KP	13	{
6d0f6bcf JCPV	14	bus_start: CONFIG_SYS_PCI_MEM_BASE,
	15	phys_start: CONFIG_SYS_PCI_MEM_PHYS,
	16	size: CONFIG_SYS_PCI_MEM_SIZE,
5e918a98 KP	17	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	18	},
	19	{
6d0f6bcf JCPV	20	bus_start: CONFIG_SYS_PCI_MMIO_BASE,
	21	phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
	22	size: CONFIG_SYS_PCI_MMIO_SIZE,
5e918a98 KP	23	flags: PCI_REGION_MEM
	24	},
	25	{
6d0f6bcf JCPV	26	bus_start: CONFIG_SYS_PCI_IO_BASE,
	27	phys_start: CONFIG_SYS_PCI_IO_PHYS,
	28	size: CONFIG_SYS_PCI_IO_SIZE,
5e918a98 KP	29	flags: PCI_REGION_IO
	30	}
	31	};
	32
7e915580 AV	33	static struct pci_region pcie_regions_0[] = {
	34	{
	35	.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
	36	.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
	37	.size = CONFIG_SYS_PCIE1_MEM_SIZE,
	38	.flags = PCI_REGION_MEM,
	39	},
	40	{
	41	.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
	42	.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
	43	.size = CONFIG_SYS_PCIE1_IO_SIZE,
	44	.flags = PCI_REGION_IO,
	45	},
	46	};
	47
	48	static struct pci_region pcie_regions_1[] = {
	49	{
	50	.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
	51	.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
	52	.size = CONFIG_SYS_PCIE2_MEM_SIZE,
	53	.flags = PCI_REGION_MEM,
	54	},
	55	{
	56	.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
	57	.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
	58	.size = CONFIG_SYS_PCIE2_IO_SIZE,
	59	.flags = PCI_REGION_IO,
	60	},
	61	};
	62
5e918a98 KP	63	void pci_init_board(void)
5e918a98 KP	64	{
6d0f6bcf	65	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
7e915580	66	volatile sysconf83xx_t *sysconf = &immr->sysconf;
5e918a98 KP	67	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
5e918a98 KP	68	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
7e915580	69	volatile law83xx_t *pcie_law = sysconf->pcielaw;
5e918a98	70	struct pci_region *reg[] = { pci_regions };
7e915580 AV	71	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
7e915580 AV	72	u32 spridr = in_be32(&immr->sysconf.spridr);
5e918a98 KP	73
	74	/* Enable all 5 PCI_CLK_OUTPUTS */
	75	clk->occr \|= 0xf8000000;
	76	udelay(2000);
	77
	78	/* Configure PCI Local Access Windows */
6d0f6bcf	79	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
5e918a98 KP	80	pci_law[0].ar = LBLAWAR_EN \| LBLAWAR_512MB;
5e918a98 KP	81
6d0f6bcf	82	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
5e918a98 KP	83	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
5e918a98 KP	84
6aa3d3bf	85	mpc83xx_pci_init(1, reg);
7e915580 AV	86
	87	/* There is no PEX in MPC8379 parts. */
	88	if (PARTID_NO_E(spridr) == SPR_8379)
	89	return;
	90
	91	/* Configure the clock for PCIE controller */
	92	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM \| SCCR_PCIEXP2CM,
	93	SCCR_PCIEXP1CM_1 \| SCCR_PCIEXP2CM_1);
	94
	95	/* Deassert the resets in the control register */
	96	out_be32(&sysconf->pecr1, 0xE0008000);
	97	out_be32(&sysconf->pecr2, 0xE0008000);
	98	udelay(2000);
	99
	100	/* Configure PCI Express Local Access Windows */
	101	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	102	out_be32(&pcie_law[0].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	103
	104	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	105	out_be32(&pcie_law[1].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	106
6aa3d3bf	107	mpc83xx_pcie_init(2, pcie_reg);
5e918a98	108	}