[people/ms/u-boot.git] / board / freescale / mpc8536ds / mpc8536ds.c

/*
 * Copyright 2008-2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
#include <miiphy.h>
#include <libfdt.h>
#include <spd_sdram.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
#include <sata.h>

#include "../common/sgmii_riser.h"

int board_early_init_f (void)
{
#ifdef CONFIG_MMC
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->pmuxcr,
			(MPC85xx_PMUXCR_SDHC_CD |
			 MPC85xx_PMUXCR_SDHC_WP));

	/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
	 * however, this erratum only applies to MPC8536 Rev1.0.
	 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
	if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
			(SVR_MIN(get_svr()) >= 0x1))
			|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
		setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
#endif
	return 0;
}

int checkboard (void)
{
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	printf("Board: MPC8536DS Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
		case PIXIS_VBOOT_LBMAP_NOR0:
			puts ("vBank: 0\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR1:
			puts ("vBank: 1\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR2:
			puts ("vBank: 2\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR3:
			puts ("vBank: 3\n");
			break;
		case PIXIS_VBOOT_LBMAP_PJET:
			puts ("Promjet\n");
			break;
		case PIXIS_VBOOT_LBMAP_NAND:
			puts ("NAND\n");
			break;
	}

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram (void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
	uint d_init;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;

#if defined (CONFIG_DDR_ECC)
	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
}

#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info;
	u32 devdisr, pordevsr;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno;

	first_free_busno = fsl_pcie_init_board(0);

#ifdef CONFIG_PCI1
	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);

	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info.regs);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}
#endif

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 1;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash + promjet */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */

	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[2];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (is_serdes_configured(SGMII_TSEC1)) {
		puts("eTSEC1 is in sgmii mode.\n");
		tsec_info[num].phyaddr = 0;
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].phyaddr = 1;
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}

#ifdef CONFIG_FSL_SGMII_RISER
	if (is_serdes_configured(SGMII_TSEC1) ||
	    is_serdes_configured(SGMII_TSEC3)) {
		fsl_sgmii_riser_init(tsec_info, num);
	}
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif

#ifdef CONFIG_HAS_FSL_MPH_USB
	fsl_fdt_fixup_dr_usb(blob, bd);
#endif

	return 0;
}
#endif
Commit	Line	Data
9490a7f1	1	/*
3d7506fa	2	* Copyright 2008-2012 Freescale Semiconductor, Inc.
9490a7f1	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
9490a7f1 KG	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
	9	#include <pci.h>
	10	#include <asm/processor.h>
	11	#include <asm/mmu.h>
7c0d4a75	12	#include <asm/cache.h>
9490a7f1	13	#include <asm/immap_85xx.h>
c8514622	14	#include <asm/fsl_pci.h>
5614e71b	15	#include <fsl_ddr_sdram.h>
9490a7f1	16	#include <asm/io.h>
54648985	17	#include <asm/fsl_serdes.h>
9490a7f1 KG	18	#include <spd.h>
	19	#include <miiphy.h>
	20	#include <libfdt.h>
	21	#include <spd_sdram.h>
	22	#include <fdt_support.h>
063c1263	23	#include <fsl_mdio.h>
2e26d837 JJ	24	#include <tsec.h>
2e26d837 JJ	25	#include <netdev.h>
54a7cc49	26	#include <sata.h>
9490a7f1	27
2e26d837	28	#include "../common/sgmii_riser.h"
9490a7f1	29
80522dc8 AF	30	int board_early_init_f (void)
	31	{
	32	#ifdef CONFIG_MMC
	33	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	34
	35	setbits_be32(&gur->pmuxcr,
ae2044d8	36	(MPC85xx_PMUXCR_SDHC_CD \|
80522dc8	37	MPC85xx_PMUXCR_SDHC_WP));
8af3d22d XX	38
	39	/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
	40	* however, this erratum only applies to MPC8536 Rev1.0.
	41	* So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
	42	if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
	43	(SVR_MIN(get_svr()) >= 0x1))
	44	\|\| (SVR_MAJ(get_svr() & 0x7) > 0x1))
	45	setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
80522dc8 AF	46	#endif
	47	return 0;
	48	}
	49
9490a7f1 KG	50	int checkboard (void)
9490a7f1 KG	51	{
6bb5b412 KG	52	u8 vboot;
	53	u8 pixis_base = (u8 )PIXIS_BASE;
	54
5d065c3e	55	printf("Board: MPC8536DS Sys ID: 0x%02x, "
6bb5b412 KG	56	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	57	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	58	in_8(pixis_base + PIXIS_PVER));
	59
	60	vboot = in_8(pixis_base + PIXIS_VBOOT);
	61	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
	62	case PIXIS_VBOOT_LBMAP_NOR0:
	63	puts ("vBank: 0\n");
	64	break;
	65	case PIXIS_VBOOT_LBMAP_NOR1:
	66	puts ("vBank: 1\n");
	67	break;
	68	case PIXIS_VBOOT_LBMAP_NOR2:
	69	puts ("vBank: 2\n");
	70	break;
	71	case PIXIS_VBOOT_LBMAP_NOR3:
	72	puts ("vBank: 3\n");
	73	break;
	74	case PIXIS_VBOOT_LBMAP_PJET:
	75	puts ("Promjet\n");
	76	break;
	77	case PIXIS_VBOOT_LBMAP_NAND:
	78	puts ("NAND\n");
	79	break;
	80	}
	81
9490a7f1 KG	82	return 0;
	83	}
	84
9490a7f1 KG	85	#if !defined(CONFIG_SPD_EEPROM)
	86	/*
	87	* Fixed sdram init -- doesn't use serial presence detect.
	88	*/
	89
	90	phys_size_t fixed_sdram (void)
	91	{
6d0f6bcf	92	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
9a17eb5b	93	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
9490a7f1 KG	94	uint d_init;
9490a7f1 KG	95
6d0f6bcf JCPV	96	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	97	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
9490a7f1	98
6d0f6bcf JCPV	99	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	100	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	101	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	102	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	103	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	104	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	105	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	106	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	107	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	108	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
9490a7f1 KG	109
9490a7f1 KG	110	#if defined (CONFIG_DDR_ECC)
6d0f6bcf JCPV	111	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	112	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	113	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
9490a7f1 KG	114	#endif
	115	asm("sync;isync");
	116
	117	udelay(500);
	118
6d0f6bcf	119	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
9490a7f1 KG	120
	121	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	122	d_init = 1;
	123	debug("DDR - 1st controller: memory initializing\n");
	124	/*
	125	* Poll until memory is initialized.
	126	* 512 Meg at 400 might hit this 200 times or so.
	127	*/
	128	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	129	udelay(1000);
	130	}
	131	debug("DDR: memory initialized\n\n");
	132	asm("sync; isync");
	133	udelay(500);
	134	#endif
	135
	136	return 512 * 1024 * 1024;
	137	}
	138
	139	#endif
	140
	141	#ifdef CONFIG_PCI1
	142	static struct pci_controller pci1_hose;
	143	#endif
	144
8a414c42 MH	145	#ifdef CONFIG_PCI
8a414c42 MH	146	void pci_init_board(void)
9490a7f1	147	{
8a414c42	148	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
5f7b31b0 KG	149	struct fsl_pci_info pci_info;
5f7b31b0 KG	150	u32 devdisr, pordevsr;
8a414c42	151	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
5f7b31b0	152	int first_free_busno;
8a414c42	153
5f7b31b0	154	first_free_busno = fsl_pcie_init_board(0);
8a414c42	155
5f7b31b0	156	#ifdef CONFIG_PCI1
8a414c42 MH	157	devdisr = in_be32(&gur->devdisr);
	158	pordevsr = in_be32(&gur->pordevsr);
	159	porpllsr = in_be32(&gur->porpllsr);
9490a7f1	160
8a414c42 MH	161	pci_speed = 66666000;
	162	pci_32 = 1;
	163	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	164	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
9490a7f1	165
9490a7f1	166	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
5f7b31b0 KG	167	SET_STD_PCI_INFO(pci_info, 1);
	168	set_next_law(pci_info.mem_phys,
	169	law_size_bits(pci_info.mem_size), pci_info.law);
	170	set_next_law(pci_info.io_phys,
	171	law_size_bits(pci_info.io_size), pci_info.law);
	172
	173	pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c	174	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
9490a7f1 KG	175	(pci_32) ? 32 : 64,
	176	(pci_speed == 33333000) ? "33" :
	177	(pci_speed == 66666000) ? "66" : "unknown",
	178	pci_clk_sel ? "sync" : "async",
	179	pci_agent ? "agent" : "host",
	180	pci_arb ? "arbiter" : "external-arbiter",
5f7b31b0	181	pci_info.regs);
9490a7f1	182
5f7b31b0	183	first_free_busno = fsl_pci_init_port(&pci_info,
8a414c42	184	&pci1_hose, first_free_busno);
9490a7f1	185	} else {
8ca78f2c	186	printf("PCI: disabled\n");
9490a7f1	187	}
8a414c42 MH	188
8a414c42 MH	189	puts("\n");
9490a7f1	190	#else
8a414c42	191	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
9490a7f1 KG	192	#endif
9490a7f1 KG	193	}
8a414c42	194	#endif
9490a7f1	195
9490a7f1 KG	196	int board_early_init_r(void)
9490a7f1 KG	197	{
6d0f6bcf	198	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	199	int flash_esel = find_tlb_idx((void *)flashbase, 1);
9490a7f1 KG	200
	201	/*
	202	* Remap Boot flash + PROMJET region to caching-inhibited
	203	* so that flash can be erased properly.
	204	*/
	205
7c0d4a75	206	/* Flush d-cache and invalidate i-cache of any FLASH data */
3cbd8231 WD	207	flush_dcache();
3cbd8231 WD	208	invalidate_icache();
9490a7f1	209
9d045682 YS	210	if (flash_esel == -1) {
	211	/* very unlikely unless something is messed up */
	212	puts("Error: Could not find TLB for FLASH BASE\n");
	213	flash_esel = 1; /* give our best effort to continue */
	214	} else {
	215	/* invalidate existing TLB entry for flash + promjet */
	216	disable_tlb(flash_esel);
	217	}
9490a7f1	218
c953ddfd	219	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
9490a7f1 KG	220	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	221	0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
	222
	223	return 0;
	224	}
	225
2e26d837 JJ	226	int board_eth_init(bd_t *bis)
	227	{
	228	#ifdef CONFIG_TSEC_ENET
063c1263	229	struct fsl_pq_mdio_info mdio_info;
2e26d837	230	struct tsec_info_struct tsec_info[2];
2e26d837	231	int num = 0;
2e26d837 JJ	232
	233	#ifdef CONFIG_TSEC1
	234	SET_STD_TSEC_INFO(tsec_info[num], 1);
058d7dc7 KG	235	if (is_serdes_configured(SGMII_TSEC1)) {
058d7dc7 KG	236	puts("eTSEC1 is in sgmii mode.\n");
2e26d837 JJ	237	tsec_info[num].phyaddr = 0;
	238	tsec_info[num].flags \|= TSEC_SGMII;
	239	}
	240	num++;
	241	#endif
	242	#ifdef CONFIG_TSEC3
	243	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	244	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	245	puts("eTSEC3 is in sgmii mode.\n");
2e26d837 JJ	246	tsec_info[num].phyaddr = 1;
	247	tsec_info[num].flags \|= TSEC_SGMII;
	248	}
	249	num++;
	250	#endif
	251
	252	if (!num) {
	253	printf("No TSECs initialized\n");
	254	return 0;
	255	}
	256
feede8b0	257	#ifdef CONFIG_FSL_SGMII_RISER
058d7dc7 KG	258	if (is_serdes_configured(SGMII_TSEC1) \|\|
058d7dc7 KG	259	is_serdes_configured(SGMII_TSEC3)) {
2e26d837	260	fsl_sgmii_riser_init(tsec_info, num);
058d7dc7	261	}
feede8b0	262	#endif
2e26d837	263
063c1263 AF	264	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	265	mdio_info.name = DEFAULT_MII_NAME;
	266	fsl_pq_mdio_init(bis, &mdio_info);
	267
2e26d837 JJ	268	tsec_eth_init(bis, tsec_info, num);
	269	#endif
	270	return pci_eth_init(bis);
	271	}
	272
9490a7f1	273	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	274	int ft_board_setup(void blob, bd_t bd)
2dba0dea	275	{
9490a7f1 KG	276	ft_cpu_setup(blob, bd);
9490a7f1 KG	277
6525d51f KG	278	FT_FSL_PCI_SETUP;
6525d51f KG	279
feede8b0 AF	280	#ifdef CONFIG_FSL_SGMII_RISER
	281	fsl_sgmii_riser_fdt_fixup(blob);
	282	#endif
3d7506fa	283
3d7506fa	284	#ifdef CONFIG_HAS_FSL_MPH_USB
a5c289b9	285	fsl_fdt_fixup_dr_usb(blob, bd);
3d7506fa	286	#endif
3d7506fa	287
e895a4b0	288	return 0;
9490a7f1 KG	289	}
9490a7f1 KG	290	#endif