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1 | /* |
2 | * Copyright 2008 Freescale Semiconductor. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <command.h> | |
25 | #include <pci.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/mmu.h> | |
28 | #include <asm/immap_85xx.h> | |
29 | #include <asm/immap_fsl_pci.h> | |
30 | #include <asm/fsl_ddr_sdram.h> | |
31 | #include <asm/io.h> | |
32 | #include <spd.h> | |
33 | #include <miiphy.h> | |
34 | #include <libfdt.h> | |
35 | #include <spd_sdram.h> | |
36 | #include <fdt_support.h> | |
37 | ||
38 | #include "../common/pixis.h" | |
39 | ||
40 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
41 | extern void ddr_enable_ecc(unsigned int dram_size); | |
42 | #endif | |
43 | ||
44 | phys_size_t fixed_sdram(void); | |
45 | ||
46 | int checkboard (void) | |
47 | { | |
48 | printf ("Board: MPC8536DS, System ID: 0x%02x, " | |
49 | "System Version: 0x%02x, FPGA Version: 0x%02x\n", | |
50 | in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), | |
51 | in8(PIXIS_BASE + PIXIS_PVER)); | |
52 | return 0; | |
53 | } | |
54 | ||
55 | phys_size_t | |
56 | initdram(int board_type) | |
57 | { | |
58 | phys_size_t dram_size = 0; | |
59 | ||
60 | puts("Initializing...."); | |
61 | ||
62 | #ifdef CONFIG_SPD_EEPROM | |
63 | dram_size = fsl_ddr_sdram(); | |
64 | ||
65 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
66 | ||
67 | dram_size *= 0x100000; | |
68 | #else | |
69 | dram_size = fixed_sdram(); | |
70 | #endif | |
71 | ||
72 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
73 | /* | |
74 | * Initialize and enable DDR ECC. | |
75 | */ | |
76 | ddr_enable_ecc(dram_size); | |
77 | #endif | |
78 | puts(" DDR: "); | |
79 | return dram_size; | |
80 | } | |
81 | ||
82 | #if !defined(CONFIG_SPD_EEPROM) | |
83 | /* | |
84 | * Fixed sdram init -- doesn't use serial presence detect. | |
85 | */ | |
86 | ||
87 | phys_size_t fixed_sdram (void) | |
88 | { | |
89 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
90 | volatile ccsr_ddr_t *ddr= &immap->im_ddr; | |
91 | uint d_init; | |
92 | ||
93 | ddr->cs0_bnds = CFG_DDR_CS0_BNDS; | |
94 | ddr->cs0_config = CFG_DDR_CS0_CONFIG; | |
95 | ||
96 | ddr->timing_cfg_3 = CFG_DDR_TIMING_3; | |
97 | ddr->timing_cfg_0 = CFG_DDR_TIMING_0; | |
98 | ddr->timing_cfg_1 = CFG_DDR_TIMING_1; | |
99 | ddr->timing_cfg_2 = CFG_DDR_TIMING_2; | |
100 | ddr->sdram_mode = CFG_DDR_MODE_1; | |
101 | ddr->sdram_mode_2 = CFG_DDR_MODE_2; | |
102 | ddr->sdram_interval = CFG_DDR_INTERVAL; | |
103 | ddr->sdram_data_init = CFG_DDR_DATA_INIT; | |
104 | ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; | |
105 | ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; | |
106 | ||
107 | #if defined (CONFIG_DDR_ECC) | |
108 | ddr->err_int_en = CFG_DDR_ERR_INT_EN; | |
109 | ddr->err_disable = CFG_DDR_ERR_DIS; | |
110 | ddr->err_sbe = CFG_DDR_SBE; | |
111 | #endif | |
112 | asm("sync;isync"); | |
113 | ||
114 | udelay(500); | |
115 | ||
116 | ddr->sdram_cfg = CFG_DDR_CONTROL; | |
117 | ||
118 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) | |
119 | d_init = 1; | |
120 | debug("DDR - 1st controller: memory initializing\n"); | |
121 | /* | |
122 | * Poll until memory is initialized. | |
123 | * 512 Meg at 400 might hit this 200 times or so. | |
124 | */ | |
125 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { | |
126 | udelay(1000); | |
127 | } | |
128 | debug("DDR: memory initialized\n\n"); | |
129 | asm("sync; isync"); | |
130 | udelay(500); | |
131 | #endif | |
132 | ||
133 | return 512 * 1024 * 1024; | |
134 | } | |
135 | ||
136 | #endif | |
137 | ||
138 | #ifdef CONFIG_PCI1 | |
139 | static struct pci_controller pci1_hose; | |
140 | #endif | |
141 | ||
142 | #ifdef CONFIG_PCIE1 | |
143 | static struct pci_controller pcie1_hose; | |
144 | #endif | |
145 | ||
146 | #ifdef CONFIG_PCIE2 | |
147 | static struct pci_controller pcie2_hose; | |
148 | #endif | |
149 | ||
150 | #ifdef CONFIG_PCIE3 | |
151 | static struct pci_controller pcie3_hose; | |
152 | #endif | |
153 | ||
154 | int first_free_busno=0; | |
155 | ||
156 | void | |
157 | pci_init_board(void) | |
158 | { | |
159 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
160 | uint devdisr = gur->devdisr; | |
161 | uint sdrs2_io_sel = | |
162 | (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; | |
163 | uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; | |
164 | uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; | |
165 | ||
166 | debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ | |
167 | host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); | |
168 | ||
169 | if (sdrs2_io_sel == 7) | |
170 | printf(" Serdes2 disalbed\n"); | |
171 | else if (sdrs2_io_sel == 4) { | |
172 | printf(" eTSEC1 is in sgmii mode.\n"); | |
173 | printf(" eTSEC3 is in sgmii mode.\n"); | |
174 | } else if (sdrs2_io_sel == 6) | |
175 | printf(" eTSEC1 is in sgmii mode.\n"); | |
176 | ||
177 | #ifdef CONFIG_PCIE3 | |
178 | { | |
179 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; | |
180 | extern void fsl_pci_init(struct pci_controller *hose); | |
181 | struct pci_controller *hose = &pcie3_hose; | |
182 | int pcie_ep = (host_agent == 1); | |
183 | int pcie_configured = (io_sel == 7); | |
184 | ||
185 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ | |
186 | printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", | |
187 | pcie_ep ? "End Point" : "Root Complex", | |
188 | (uint)pci); | |
189 | if (pci->pme_msg_det) { | |
190 | pci->pme_msg_det = 0xffffffff; | |
191 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
192 | } | |
193 | printf ("\n"); | |
194 | ||
195 | /* inbound */ | |
196 | pci_set_region(hose->regions + 0, | |
197 | CFG_PCI_MEMORY_BUS, | |
198 | CFG_PCI_MEMORY_PHYS, | |
199 | CFG_PCI_MEMORY_SIZE, | |
200 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
201 | ||
202 | /* outbound memory */ | |
203 | pci_set_region(hose->regions + 1, | |
204 | CFG_PCIE3_MEM_BASE, | |
205 | CFG_PCIE3_MEM_PHYS, | |
206 | CFG_PCIE3_MEM_SIZE, | |
207 | PCI_REGION_MEM); | |
208 | ||
209 | /* outbound io */ | |
210 | pci_set_region(hose->regions + 2, | |
211 | CFG_PCIE3_IO_BASE, | |
212 | CFG_PCIE3_IO_PHYS, | |
213 | CFG_PCIE3_IO_SIZE, | |
214 | PCI_REGION_IO); | |
215 | ||
216 | hose->region_count = 3; | |
217 | ||
218 | hose->first_busno=first_free_busno; | |
219 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
220 | ||
221 | fsl_pci_init(hose); | |
222 | ||
223 | first_free_busno=hose->last_busno+1; | |
224 | printf (" PCIE3 on bus %02x - %02x\n", | |
225 | hose->first_busno,hose->last_busno); | |
226 | } else { | |
227 | printf (" PCIE3: disabled\n"); | |
228 | } | |
229 | ||
230 | } | |
231 | #else | |
232 | gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ | |
233 | #endif | |
234 | ||
235 | #ifdef CONFIG_PCIE1 | |
236 | { | |
237 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; | |
238 | extern void fsl_pci_init(struct pci_controller *hose); | |
239 | struct pci_controller *hose = &pcie1_hose; | |
240 | int pcie_ep = (host_agent == 5); | |
241 | int pcie_configured = (io_sel == 2 || io_sel == 3 | |
242 | || io_sel == 5 || io_sel == 7); | |
243 | ||
244 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ | |
245 | printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", | |
246 | pcie_ep ? "End Point" : "Root Complex", | |
247 | (uint)pci); | |
248 | if (pci->pme_msg_det) { | |
249 | pci->pme_msg_det = 0xffffffff; | |
250 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
251 | } | |
252 | printf ("\n"); | |
253 | ||
254 | /* inbound */ | |
255 | pci_set_region(hose->regions + 0, | |
256 | CFG_PCI_MEMORY_BUS, | |
257 | CFG_PCI_MEMORY_PHYS, | |
258 | CFG_PCI_MEMORY_SIZE, | |
259 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
260 | ||
261 | /* outbound memory */ | |
262 | pci_set_region(hose->regions + 1, | |
263 | CFG_PCIE1_MEM_BASE, | |
264 | CFG_PCIE1_MEM_PHYS, | |
265 | CFG_PCIE1_MEM_SIZE, | |
266 | PCI_REGION_MEM); | |
267 | ||
268 | /* outbound io */ | |
269 | pci_set_region(hose->regions + 2, | |
270 | CFG_PCIE1_IO_BASE, | |
271 | CFG_PCIE1_IO_PHYS, | |
272 | CFG_PCIE1_IO_SIZE, | |
273 | PCI_REGION_IO); | |
274 | ||
275 | hose->region_count = 3; | |
276 | #ifdef CFG_PCIE1_MEM_BASE2 | |
277 | /* outbound memory */ | |
278 | pci_set_region(hose->regions + 3, | |
279 | CFG_PCIE1_MEM_BASE2, | |
280 | CFG_PCIE1_MEM_PHYS2, | |
281 | CFG_PCIE1_MEM_SIZE2, | |
282 | PCI_REGION_MEM); | |
283 | hose->region_count++; | |
284 | #endif | |
285 | hose->first_busno=first_free_busno; | |
286 | ||
287 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
288 | ||
289 | fsl_pci_init(hose); | |
290 | ||
291 | first_free_busno=hose->last_busno+1; | |
292 | printf(" PCIE1 on bus %02x - %02x\n", | |
293 | hose->first_busno,hose->last_busno); | |
294 | ||
295 | } else { | |
296 | printf (" PCIE1: disabled\n"); | |
297 | } | |
298 | ||
299 | } | |
300 | #else | |
301 | gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ | |
302 | #endif | |
303 | ||
304 | #ifdef CONFIG_PCIE2 | |
305 | { | |
306 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; | |
307 | extern void fsl_pci_init(struct pci_controller *hose); | |
308 | struct pci_controller *hose = &pcie2_hose; | |
309 | int pcie_ep = (host_agent == 3); | |
310 | int pcie_configured = (io_sel == 5 || io_sel == 7); | |
311 | ||
312 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ | |
313 | printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", | |
314 | pcie_ep ? "End Point" : "Root Complex", | |
315 | (uint)pci); | |
316 | if (pci->pme_msg_det) { | |
317 | pci->pme_msg_det = 0xffffffff; | |
318 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); | |
319 | } | |
320 | printf ("\n"); | |
321 | ||
322 | /* inbound */ | |
323 | pci_set_region(hose->regions + 0, | |
324 | CFG_PCI_MEMORY_BUS, | |
325 | CFG_PCI_MEMORY_PHYS, | |
326 | CFG_PCI_MEMORY_SIZE, | |
327 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
328 | ||
329 | /* outbound memory */ | |
330 | pci_set_region(hose->regions + 1, | |
331 | CFG_PCIE2_MEM_BASE, | |
332 | CFG_PCIE2_MEM_PHYS, | |
333 | CFG_PCIE2_MEM_SIZE, | |
334 | PCI_REGION_MEM); | |
335 | ||
336 | /* outbound io */ | |
337 | pci_set_region(hose->regions + 2, | |
338 | CFG_PCIE2_IO_BASE, | |
339 | CFG_PCIE2_IO_PHYS, | |
340 | CFG_PCIE2_IO_SIZE, | |
341 | PCI_REGION_IO); | |
342 | ||
343 | hose->region_count = 3; | |
344 | #ifdef CFG_PCIE2_MEM_BASE2 | |
345 | /* outbound memory */ | |
346 | pci_set_region(hose->regions + 3, | |
347 | CFG_PCIE2_MEM_BASE2, | |
348 | CFG_PCIE2_MEM_PHYS2, | |
349 | CFG_PCIE2_MEM_SIZE2, | |
350 | PCI_REGION_MEM); | |
351 | hose->region_count++; | |
352 | #endif | |
353 | hose->first_busno=first_free_busno; | |
354 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
355 | ||
356 | fsl_pci_init(hose); | |
357 | first_free_busno=hose->last_busno+1; | |
358 | printf (" PCIE2 on bus %02x - %02x\n", | |
359 | hose->first_busno,hose->last_busno); | |
360 | ||
361 | } else { | |
362 | printf (" PCIE2: disabled\n"); | |
363 | } | |
364 | ||
365 | } | |
366 | #else | |
367 | gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ | |
368 | #endif | |
369 | ||
370 | ||
371 | #ifdef CONFIG_PCI1 | |
372 | { | |
373 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; | |
374 | extern void fsl_pci_init(struct pci_controller *hose); | |
375 | struct pci_controller *hose = &pci1_hose; | |
376 | ||
377 | uint pci_agent = (host_agent == 6); | |
378 | uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ | |
379 | uint pci_32 = 1; | |
380 | uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ | |
381 | uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ | |
382 | ||
383 | ||
384 | if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { | |
385 | printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", | |
386 | (pci_32) ? 32 : 64, | |
387 | (pci_speed == 33333000) ? "33" : | |
388 | (pci_speed == 66666000) ? "66" : "unknown", | |
389 | pci_clk_sel ? "sync" : "async", | |
390 | pci_agent ? "agent" : "host", | |
391 | pci_arb ? "arbiter" : "external-arbiter", | |
392 | (uint)pci | |
393 | ); | |
394 | ||
395 | /* inbound */ | |
396 | pci_set_region(hose->regions + 0, | |
397 | CFG_PCI_MEMORY_BUS, | |
398 | CFG_PCI_MEMORY_PHYS, | |
399 | CFG_PCI_MEMORY_SIZE, | |
400 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
401 | ||
402 | /* outbound memory */ | |
403 | pci_set_region(hose->regions + 1, | |
404 | CFG_PCI1_MEM_BASE, | |
405 | CFG_PCI1_MEM_PHYS, | |
406 | CFG_PCI1_MEM_SIZE, | |
407 | PCI_REGION_MEM); | |
408 | ||
409 | /* outbound io */ | |
410 | pci_set_region(hose->regions + 2, | |
411 | CFG_PCI1_IO_BASE, | |
412 | CFG_PCI1_IO_PHYS, | |
413 | CFG_PCI1_IO_SIZE, | |
414 | PCI_REGION_IO); | |
415 | hose->region_count = 3; | |
416 | #ifdef CFG_PCI1_MEM_BASE2 | |
417 | /* outbound memory */ | |
418 | pci_set_region(hose->regions + 3, | |
419 | CFG_PCI1_MEM_BASE2, | |
420 | CFG_PCI1_MEM_PHYS2, | |
421 | CFG_PCI1_MEM_SIZE2, | |
422 | PCI_REGION_MEM); | |
423 | hose->region_count++; | |
424 | #endif | |
425 | hose->first_busno=first_free_busno; | |
426 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); | |
427 | ||
428 | fsl_pci_init(hose); | |
429 | first_free_busno=hose->last_busno+1; | |
430 | printf ("PCI on bus %02x - %02x\n", | |
431 | hose->first_busno,hose->last_busno); | |
432 | } else { | |
433 | printf (" PCI: disabled\n"); | |
434 | } | |
435 | } | |
436 | #else | |
437 | gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ | |
438 | #endif | |
439 | } | |
440 | ||
441 | ||
442 | int board_early_init_r(void) | |
443 | { | |
444 | unsigned int i; | |
445 | const unsigned int flashbase = CFG_FLASH_BASE; | |
446 | const u8 flash_esel = 1; | |
447 | ||
448 | /* | |
449 | * Remap Boot flash + PROMJET region to caching-inhibited | |
450 | * so that flash can be erased properly. | |
451 | */ | |
452 | ||
453 | /* Invalidate any remaining lines of the flash from caches. */ | |
454 | for (i = 0; i < 256*1024*1024; i+=32) { | |
455 | asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); | |
456 | asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); | |
457 | } | |
458 | ||
459 | /* invalidate existing TLB entry for flash + promjet */ | |
460 | disable_tlb(flash_esel); | |
461 | ||
462 | set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ | |
463 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ | |
464 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | #ifdef CONFIG_GET_CLK_FROM_ICS307 | |
470 | /* decode S[0-2] to Output Divider (OD) */ | |
471 | static unsigned char | |
472 | ics307_S_to_OD[] = { | |
473 | 10, 2, 8, 4, 5, 7, 3, 6 | |
474 | }; | |
475 | ||
476 | /* Calculate frequency being generated by ICS307-02 clock chip based upon | |
477 | * the control bytes being programmed into it. */ | |
478 | /* XXX: This function should probably go into a common library */ | |
479 | static unsigned long | |
480 | ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) | |
481 | { | |
482 | const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; | |
483 | unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); | |
484 | unsigned long RDW = cw2 & 0x7F; | |
485 | unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; | |
486 | unsigned long freq; | |
487 | ||
488 | /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ | |
489 | ||
490 | /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 | |
491 | * cw1: V8 V7 V6 V5 V4 V3 V2 V1 | |
492 | * cw2: V0 R6 R5 R4 R3 R2 R1 R0 | |
493 | * | |
494 | * R6:R0 = Reference Divider Word (RDW) | |
495 | * V8:V0 = VCO Divider Word (VDW) | |
496 | * S2:S0 = Output Divider Select (OD) | |
497 | * F1:F0 = Function of CLK2 Output | |
498 | * TTL = duty cycle | |
499 | * C1:C0 = internal load capacitance for cyrstal | |
500 | */ | |
501 | ||
502 | /* Adding 1 to get a "nicely" rounded number, but this needs | |
503 | * more tweaking to get a "properly" rounded number. */ | |
504 | ||
505 | freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); | |
506 | ||
507 | debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, | |
508 | freq); | |
509 | return freq; | |
510 | } | |
511 | ||
512 | unsigned long | |
513 | get_board_sys_clk(ulong dummy) | |
514 | { | |
515 | return ics307_clk_freq ( | |
516 | in8(PIXIS_BASE + PIXIS_VSYSCLK0), | |
517 | in8(PIXIS_BASE + PIXIS_VSYSCLK1), | |
518 | in8(PIXIS_BASE + PIXIS_VSYSCLK2) | |
519 | ); | |
520 | } | |
521 | ||
522 | unsigned long | |
523 | get_board_ddr_clk(ulong dummy) | |
524 | { | |
525 | return ics307_clk_freq ( | |
526 | in8(PIXIS_BASE + PIXIS_VDDRCLK0), | |
527 | in8(PIXIS_BASE + PIXIS_VDDRCLK1), | |
528 | in8(PIXIS_BASE + PIXIS_VDDRCLK2) | |
529 | ); | |
530 | } | |
531 | #else | |
532 | unsigned long | |
533 | get_board_sys_clk(ulong dummy) | |
534 | { | |
535 | u8 i; | |
536 | ulong val = 0; | |
537 | ||
538 | i = in8(PIXIS_BASE + PIXIS_SPD); | |
539 | i &= 0x07; | |
540 | ||
541 | switch (i) { | |
542 | case 0: | |
543 | val = 33333333; | |
544 | break; | |
545 | case 1: | |
546 | val = 40000000; | |
547 | break; | |
548 | case 2: | |
549 | val = 50000000; | |
550 | break; | |
551 | case 3: | |
552 | val = 66666666; | |
553 | break; | |
554 | case 4: | |
555 | val = 83333333; | |
556 | break; | |
557 | case 5: | |
558 | val = 100000000; | |
559 | break; | |
560 | case 6: | |
561 | val = 133333333; | |
562 | break; | |
563 | case 7: | |
564 | val = 166666666; | |
565 | break; | |
566 | } | |
567 | ||
568 | return val; | |
569 | } | |
570 | ||
571 | unsigned long | |
572 | get_board_ddr_clk(ulong dummy) | |
573 | { | |
574 | u8 i; | |
575 | ulong val = 0; | |
576 | ||
577 | i = in8(PIXIS_BASE + PIXIS_SPD); | |
578 | i &= 0x38; | |
579 | i >>= 3; | |
580 | ||
581 | switch (i) { | |
582 | case 0: | |
583 | val = 33333333; | |
584 | break; | |
585 | case 1: | |
586 | val = 40000000; | |
587 | break; | |
588 | case 2: | |
589 | val = 50000000; | |
590 | break; | |
591 | case 3: | |
592 | val = 66666666; | |
593 | break; | |
594 | case 4: | |
595 | val = 83333333; | |
596 | break; | |
597 | case 5: | |
598 | val = 100000000; | |
599 | break; | |
600 | case 6: | |
601 | val = 133333333; | |
602 | break; | |
603 | case 7: | |
604 | val = 166666666; | |
605 | break; | |
606 | } | |
607 | return val; | |
608 | } | |
609 | #endif | |
610 | ||
374b9038 | 611 | int is_sata_supported(void) |
0f8cbc18 JJ |
612 | { |
613 | volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); | |
0f8cbc18 JJ |
614 | uint sdrs2_io_sel = |
615 | (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; | |
616 | if (sdrs2_io_sel & 0x04) | |
617 | return 0; | |
618 | ||
619 | return 1; | |
620 | } | |
621 | ||
9490a7f1 KG |
622 | #if defined(CONFIG_OF_BOARD_SETUP) |
623 | void | |
624 | ft_board_setup(void *blob, bd_t *bd) | |
625 | { | |
626 | int node, tmp[2]; | |
627 | const char *path; | |
628 | ||
629 | ft_cpu_setup(blob, bd); | |
630 | ||
631 | node = fdt_path_offset(blob, "/aliases"); | |
632 | tmp[0] = 0; | |
633 | if (node >= 0) { | |
634 | #ifdef CONFIG_PCI1 | |
635 | path = fdt_getprop(blob, node, "pci0", NULL); | |
636 | if (path) { | |
637 | tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; | |
638 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
639 | } | |
640 | #endif | |
641 | #ifdef CONFIG_PCIE2 | |
642 | path = fdt_getprop(blob, node, "pci1", NULL); | |
643 | if (path) { | |
644 | tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; | |
645 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
646 | } | |
647 | #endif | |
648 | #ifdef CONFIG_PCIE1 | |
649 | path = fdt_getprop(blob, node, "pci2", NULL); | |
650 | if (path) { | |
651 | tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; | |
652 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
653 | } | |
654 | #endif | |
655 | #ifdef CONFIG_PCIE3 | |
656 | path = fdt_getprop(blob, node, "pci3", NULL); | |
657 | if (path) { | |
658 | tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; | |
659 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
660 | } | |
661 | #endif | |
662 | } | |
663 | } | |
664 | #endif |