[thirdparty/u-boot.git] / board / freescale / mpc8536ds / mpc8536ds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2008-2012 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <command.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <spd_sdram.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
#include <sata.h>

#include "../common/sgmii_riser.h"

int board_early_init_f (void)
{
#ifdef CONFIG_MMC
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->pmuxcr,
			(MPC85xx_PMUXCR_SDHC_CD |
			 MPC85xx_PMUXCR_SDHC_WP));

	/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
	 * however, this erratum only applies to MPC8536 Rev1.0.
	 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
	if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
			(SVR_MIN(get_svr()) >= 0x1))
			|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
		setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
#endif
	return 0;
}

int checkboard (void)
{
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	printf("Board: MPC8536DS Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
		case PIXIS_VBOOT_LBMAP_NOR0:
			puts ("vBank: 0\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR1:
			puts ("vBank: 1\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR2:
			puts ("vBank: 2\n");
			break;
		case PIXIS_VBOOT_LBMAP_NOR3:
			puts ("vBank: 3\n");
			break;
		case PIXIS_VBOOT_LBMAP_PJET:
			puts ("Promjet\n");
			break;
		case PIXIS_VBOOT_LBMAP_NAND:
			puts ("NAND\n");
			break;
	}

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram (void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
	uint d_init;

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;

#if defined (CONFIG_DDR_ECC)
	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
		udelay(1000);
	}
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
}

#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info;
	u32 devdisr, pordevsr;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno;

	first_free_busno = fsl_pcie_init_board(0);

#ifdef CONFIG_PCI1
	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);

	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info.regs);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}
#endif

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 1;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash + promjet */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,	/* tlb, epn, rpn */
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,	/* perms, wimge */
		0, flash_esel, BOOKE_PAGESZ_256M, 1);	/* ts, esel, tsize, iprot */

	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[2];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (is_serdes_configured(SGMII_TSEC1)) {
		puts("eTSEC1 is in sgmii mode.\n");
		tsec_info[num].phyaddr = 0;
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].phyaddr = 1;
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}

#ifdef CONFIG_FSL_SGMII_RISER
	if (is_serdes_configured(SGMII_TSEC1) ||
	    is_serdes_configured(SGMII_TSEC3)) {
		fsl_sgmii_riser_init(tsec_info, num);
	}
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif

#ifdef CONFIG_HAS_FSL_MPH_USB
	fsl_fdt_fixup_dr_usb(blob, bd);
#endif

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
9490a7f1	2	/*
3d7506fa	3	* Copyright 2008-2012 Freescale Semiconductor, Inc.
9490a7f1 KG	4	*/
	5
	6	#include <common.h>
	7	#include <command.h>
5255932f	8	#include <init.h>
90526e9f	9	#include <net.h>
9490a7f1 KG	10	#include <pci.h>
	11	#include <asm/processor.h>
	12	#include <asm/mmu.h>
7c0d4a75	13	#include <asm/cache.h>
9490a7f1	14	#include <asm/immap_85xx.h>
c8514622	15	#include <asm/fsl_pci.h>
5614e71b	16	#include <fsl_ddr_sdram.h>
9490a7f1	17	#include <asm/io.h>
54648985	18	#include <asm/fsl_serdes.h>
9490a7f1 KG	19	#include <spd.h>
9490a7f1 KG	20	#include <miiphy.h>
b08c8c48	21	#include <linux/libfdt.h>
9490a7f1 KG	22	#include <spd_sdram.h>
9490a7f1 KG	23	#include <fdt_support.h>
063c1263	24	#include <fsl_mdio.h>
2e26d837 JJ	25	#include <tsec.h>
2e26d837 JJ	26	#include <netdev.h>
54a7cc49	27	#include <sata.h>
9490a7f1	28
2e26d837	29	#include "../common/sgmii_riser.h"
9490a7f1	30
80522dc8 AF	31	int board_early_init_f (void)
	32	{
	33	#ifdef CONFIG_MMC
	34	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	35
	36	setbits_be32(&gur->pmuxcr,
ae2044d8	37	(MPC85xx_PMUXCR_SDHC_CD \|
80522dc8	38	MPC85xx_PMUXCR_SDHC_WP));
8af3d22d XX	39
	40	/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
	41	* however, this erratum only applies to MPC8536 Rev1.0.
	42	* So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
	43	if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
	44	(SVR_MIN(get_svr()) >= 0x1))
	45	\|\| (SVR_MAJ(get_svr() & 0x7) > 0x1))
	46	setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
80522dc8 AF	47	#endif
	48	return 0;
	49	}
	50
9490a7f1 KG	51	int checkboard (void)
9490a7f1 KG	52	{
6bb5b412 KG	53	u8 vboot;
	54	u8 pixis_base = (u8 )PIXIS_BASE;
	55
5d065c3e	56	printf("Board: MPC8536DS Sys ID: 0x%02x, "
6bb5b412 KG	57	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	58	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	59	in_8(pixis_base + PIXIS_PVER));
	60
	61	vboot = in_8(pixis_base + PIXIS_VBOOT);
	62	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
	63	case PIXIS_VBOOT_LBMAP_NOR0:
	64	puts ("vBank: 0\n");
	65	break;
	66	case PIXIS_VBOOT_LBMAP_NOR1:
	67	puts ("vBank: 1\n");
	68	break;
	69	case PIXIS_VBOOT_LBMAP_NOR2:
	70	puts ("vBank: 2\n");
	71	break;
	72	case PIXIS_VBOOT_LBMAP_NOR3:
	73	puts ("vBank: 3\n");
	74	break;
	75	case PIXIS_VBOOT_LBMAP_PJET:
	76	puts ("Promjet\n");
	77	break;
	78	case PIXIS_VBOOT_LBMAP_NAND:
	79	puts ("NAND\n");
	80	break;
	81	}
	82
9490a7f1 KG	83	return 0;
	84	}
	85
9490a7f1 KG	86	#if !defined(CONFIG_SPD_EEPROM)
	87	/*
	88	* Fixed sdram init -- doesn't use serial presence detect.
	89	*/
	90
	91	phys_size_t fixed_sdram (void)
	92	{
6d0f6bcf	93	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
9a17eb5b	94	struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
9490a7f1 KG	95	uint d_init;
9490a7f1 KG	96
6d0f6bcf JCPV	97	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
6d0f6bcf JCPV	98	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
9490a7f1	99
6d0f6bcf JCPV	100	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	101	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	102	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	103	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	104	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	105	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	106	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	107	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	108	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	109	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
9490a7f1 KG	110
9490a7f1 KG	111	#if defined (CONFIG_DDR_ECC)
6d0f6bcf JCPV	112	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
	113	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
	114	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
9490a7f1 KG	115	#endif
	116	asm("sync;isync");
	117
	118	udelay(500);
	119
6d0f6bcf	120	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
9490a7f1 KG	121
	122	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	123	d_init = 1;
	124	debug("DDR - 1st controller: memory initializing\n");
	125	/*
	126	* Poll until memory is initialized.
	127	* 512 Meg at 400 might hit this 200 times or so.
	128	*/
	129	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
	130	udelay(1000);
	131	}
	132	debug("DDR: memory initialized\n\n");
	133	asm("sync; isync");
	134	udelay(500);
	135	#endif
	136
	137	return 512 * 1024 * 1024;
	138	}
	139
	140	#endif
	141
	142	#ifdef CONFIG_PCI1
	143	static struct pci_controller pci1_hose;
	144	#endif
	145
8a414c42 MH	146	#ifdef CONFIG_PCI
8a414c42 MH	147	void pci_init_board(void)
9490a7f1	148	{
8a414c42	149	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
5f7b31b0 KG	150	struct fsl_pci_info pci_info;
5f7b31b0 KG	151	u32 devdisr, pordevsr;
8a414c42	152	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
5f7b31b0	153	int first_free_busno;
8a414c42	154
5f7b31b0	155	first_free_busno = fsl_pcie_init_board(0);
8a414c42	156
5f7b31b0	157	#ifdef CONFIG_PCI1
8a414c42 MH	158	devdisr = in_be32(&gur->devdisr);
	159	pordevsr = in_be32(&gur->pordevsr);
	160	porpllsr = in_be32(&gur->porpllsr);
9490a7f1	161
8a414c42 MH	162	pci_speed = 66666000;
	163	pci_32 = 1;
	164	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	165	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
9490a7f1	166
9490a7f1	167	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
5f7b31b0 KG	168	SET_STD_PCI_INFO(pci_info, 1);
	169	set_next_law(pci_info.mem_phys,
	170	law_size_bits(pci_info.mem_size), pci_info.law);
	171	set_next_law(pci_info.io_phys,
	172	law_size_bits(pci_info.io_size), pci_info.law);
	173
	174	pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c	175	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
9490a7f1 KG	176	(pci_32) ? 32 : 64,
	177	(pci_speed == 33333000) ? "33" :
	178	(pci_speed == 66666000) ? "66" : "unknown",
	179	pci_clk_sel ? "sync" : "async",
	180	pci_agent ? "agent" : "host",
	181	pci_arb ? "arbiter" : "external-arbiter",
5f7b31b0	182	pci_info.regs);
9490a7f1	183
5f7b31b0	184	first_free_busno = fsl_pci_init_port(&pci_info,
8a414c42	185	&pci1_hose, first_free_busno);
9490a7f1	186	} else {
8ca78f2c	187	printf("PCI: disabled\n");
9490a7f1	188	}
8a414c42 MH	189
8a414c42 MH	190	puts("\n");
9490a7f1	191	#else
8a414c42	192	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
9490a7f1 KG	193	#endif
9490a7f1 KG	194	}
8a414c42	195	#endif
9490a7f1	196
9490a7f1 KG	197	int board_early_init_r(void)
9490a7f1 KG	198	{
6d0f6bcf	199	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	200	int flash_esel = find_tlb_idx((void *)flashbase, 1);
9490a7f1 KG	201
	202	/*
	203	* Remap Boot flash + PROMJET region to caching-inhibited
	204	* so that flash can be erased properly.
	205	*/
	206
7c0d4a75	207	/* Flush d-cache and invalidate i-cache of any FLASH data */
3cbd8231 WD	208	flush_dcache();
3cbd8231 WD	209	invalidate_icache();
9490a7f1	210
9d045682 YS	211	if (flash_esel == -1) {
	212	/* very unlikely unless something is messed up */
	213	puts("Error: Could not find TLB for FLASH BASE\n");
	214	flash_esel = 1; /* give our best effort to continue */
	215	} else {
	216	/* invalidate existing TLB entry for flash + promjet */
	217	disable_tlb(flash_esel);
	218	}
9490a7f1	219
c953ddfd	220	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
9490a7f1 KG	221	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G, /* perms, wimge */
	222	0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
	223
	224	return 0;
	225	}
	226
2e26d837 JJ	227	int board_eth_init(bd_t *bis)
	228	{
	229	#ifdef CONFIG_TSEC_ENET
063c1263	230	struct fsl_pq_mdio_info mdio_info;
2e26d837	231	struct tsec_info_struct tsec_info[2];
2e26d837	232	int num = 0;
2e26d837 JJ	233
	234	#ifdef CONFIG_TSEC1
	235	SET_STD_TSEC_INFO(tsec_info[num], 1);
058d7dc7 KG	236	if (is_serdes_configured(SGMII_TSEC1)) {
058d7dc7 KG	237	puts("eTSEC1 is in sgmii mode.\n");
2e26d837 JJ	238	tsec_info[num].phyaddr = 0;
	239	tsec_info[num].flags \|= TSEC_SGMII;
	240	}
	241	num++;
	242	#endif
	243	#ifdef CONFIG_TSEC3
	244	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	245	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	246	puts("eTSEC3 is in sgmii mode.\n");
2e26d837 JJ	247	tsec_info[num].phyaddr = 1;
	248	tsec_info[num].flags \|= TSEC_SGMII;
	249	}
	250	num++;
	251	#endif
	252
	253	if (!num) {
	254	printf("No TSECs initialized\n");
	255	return 0;
	256	}
	257
feede8b0	258	#ifdef CONFIG_FSL_SGMII_RISER
058d7dc7 KG	259	if (is_serdes_configured(SGMII_TSEC1) \|\|
058d7dc7 KG	260	is_serdes_configured(SGMII_TSEC3)) {
2e26d837	261	fsl_sgmii_riser_init(tsec_info, num);
058d7dc7	262	}
feede8b0	263	#endif
2e26d837	264
063c1263 AF	265	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	266	mdio_info.name = DEFAULT_MII_NAME;
	267	fsl_pq_mdio_init(bis, &mdio_info);
	268
2e26d837 JJ	269	tsec_eth_init(bis, tsec_info, num);
	270	#endif
	271	return pci_eth_init(bis);
	272	}
	273
9490a7f1	274	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	275	int ft_board_setup(void blob, bd_t bd)
2dba0dea	276	{
9490a7f1 KG	277	ft_cpu_setup(blob, bd);
9490a7f1 KG	278
6525d51f KG	279	FT_FSL_PCI_SETUP;
6525d51f KG	280
feede8b0 AF	281	#ifdef CONFIG_FSL_SGMII_RISER
	282	fsl_sgmii_riser_fdt_fixup(blob);
	283	#endif
3d7506fa	284
3d7506fa	285	#ifdef CONFIG_HAS_FSL_MPH_USB
a5c289b9	286	fsl_fdt_fixup_dr_usb(blob, bd);
3d7506fa	287	#endif
3d7506fa	288
e895a4b0	289	return 0;
9490a7f1 KG	290	}
9490a7f1 KG	291	#endif