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Commit | Line | Data |
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9617c8d4 | 1 | /* |
0ac6f8b7 | 2 | * Copyright 2004 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003, Motorola Inc. |
4 | * Xianghua Xiao, (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
42d1f039 WD |
9 | */ |
10 | ||
11 | ||
42d1f039 | 12 | #include <common.h> |
9aea9530 | 13 | #include <pci.h> |
42d1f039 | 14 | #include <asm/processor.h> |
9617c8d4 | 15 | #include <asm/mmu.h> |
42d1f039 | 16 | #include <asm/immap_85xx.h> |
5614e71b | 17 | #include <fsl_ddr_sdram.h> |
0fd5ec66 KG |
18 | #include <libfdt.h> |
19 | #include <fdt_support.h> | |
40d5fa35 | 20 | |
d9b94f28 | 21 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
0ac6f8b7 | 22 | extern void ddr_enable_ecc(unsigned int dram_size); |
97d80fc3 WD |
23 | #endif |
24 | ||
9aea9530 | 25 | void local_bus_init(void); |
97d80fc3 | 26 | |
42d1f039 WD |
27 | int checkboard (void) |
28 | { | |
97d80fc3 | 29 | puts("Board: ADS\n"); |
0ac6f8b7 WD |
30 | |
31 | #ifdef CONFIG_PCI | |
8ca78f2c | 32 | printf("PCI1: 32 bit, %d MHz (compiled)\n", |
0ac6f8b7 WD |
33 | CONFIG_SYS_CLK_FREQ / 1000000); |
34 | #else | |
8ca78f2c | 35 | printf("PCI1: disabled\n"); |
0ac6f8b7 WD |
36 | #endif |
37 | ||
9aea9530 WD |
38 | /* |
39 | * Initialize local bus. | |
40 | */ | |
41 | local_bus_init(); | |
42 | ||
97d80fc3 | 43 | return 0; |
42d1f039 WD |
44 | } |
45 | ||
0ac6f8b7 | 46 | /* |
9aea9530 | 47 | * Initialize Local Bus |
0ac6f8b7 WD |
48 | */ |
49 | ||
9aea9530 WD |
50 | void |
51 | local_bus_init(void) | |
0ac6f8b7 | 52 | { |
6d0f6bcf | 53 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
f51cdaf1 | 54 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
0ac6f8b7 | 55 | |
9aea9530 WD |
56 | uint clkdiv; |
57 | uint lbc_hz; | |
58 | sys_info_t sysinfo; | |
0ac6f8b7 WD |
59 | |
60 | /* | |
9aea9530 WD |
61 | * Errata LBC11. |
62 | * Fix Local Bus clock glitch when DLL is enabled. | |
0ac6f8b7 | 63 | * |
8ed44d91 WD |
64 | * If localbus freq is < 66MHz, DLL bypass mode must be used. |
65 | * If localbus freq is > 133MHz, DLL can be safely enabled. | |
9aea9530 | 66 | * Between 66 and 133, the DLL is enabled with an override workaround. |
0ac6f8b7 | 67 | */ |
9aea9530 WD |
68 | |
69 | get_sys_info(&sysinfo); | |
a5d212a2 | 70 | clkdiv = lbc->lcrr & LCRR_CLKDIV; |
997399fa | 71 | lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; |
9aea9530 WD |
72 | |
73 | if (lbc_hz < 66) { | |
a2af6a7a | 74 | lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ |
9aea9530 WD |
75 | |
76 | } else if (lbc_hz >= 133) { | |
a2af6a7a | 77 | lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
0ac6f8b7 | 78 | |
42d1f039 | 79 | } else { |
0ac6f8b7 WD |
80 | /* |
81 | * On REV1 boards, need to change CLKDIV before enable DLL. | |
82 | * Default CLKDIV is 8, change it to 4 temporarily. | |
83 | */ | |
9aea9530 | 84 | uint pvr = get_pvr(); |
0ac6f8b7 | 85 | uint temp_lbcdll = 0; |
97d80fc3 WD |
86 | |
87 | if (pvr == PVR_85xx_REV1) { | |
9aea9530 | 88 | /* FIXME: Justify the high bit here. */ |
0ac6f8b7 | 89 | lbc->lcrr = 0x10000004; |
97d80fc3 | 90 | } |
0ac6f8b7 | 91 | |
a2af6a7a | 92 | lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
9aea9530 WD |
93 | udelay(200); |
94 | ||
95 | /* | |
96 | * Sample LBC DLL ctrl reg, upshift it to set the | |
97 | * override bits. | |
98 | */ | |
42d1f039 | 99 | temp_lbcdll = gur->lbcdllcr; |
9aea9530 WD |
100 | gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
101 | asm("sync;isync;msync"); | |
42d1f039 | 102 | } |
9aea9530 WD |
103 | } |
104 | ||
105 | ||
106 | /* | |
107 | * Initialize SDRAM memory on the Local Bus. | |
108 | */ | |
70961ba4 | 109 | void lbc_sdram_init(void) |
9aea9530 | 110 | { |
f51cdaf1 | 111 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
6d0f6bcf | 112 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
9aea9530 | 113 | |
7ea3871e BB |
114 | puts("LBC SDRAM: "); |
115 | print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, | |
116 | "\n "); | |
0ac6f8b7 WD |
117 | |
118 | /* | |
119 | * Setup SDRAM Base and Option Registers | |
120 | */ | |
f51cdaf1 BB |
121 | set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); |
122 | set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); | |
6d0f6bcf | 123 | lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
9aea9530 | 124 | asm("msync"); |
0ac6f8b7 | 125 | |
6d0f6bcf JCPV |
126 | lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
127 | lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; | |
9aea9530 | 128 | asm("sync"); |
0ac6f8b7 WD |
129 | |
130 | /* | |
131 | * Configure the SDRAM controller. | |
132 | */ | |
6d0f6bcf | 133 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; |
9aea9530 | 134 | asm("sync"); |
0ac6f8b7 | 135 | *sdram_addr = 0xff; |
9aea9530 WD |
136 | ppcDcbf((unsigned long) sdram_addr); |
137 | udelay(100); | |
0ac6f8b7 | 138 | |
6d0f6bcf | 139 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; |
9aea9530 | 140 | asm("sync"); |
0ac6f8b7 | 141 | *sdram_addr = 0xff; |
9aea9530 WD |
142 | ppcDcbf((unsigned long) sdram_addr); |
143 | udelay(100); | |
0ac6f8b7 | 144 | |
6d0f6bcf | 145 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; |
9aea9530 | 146 | asm("sync"); |
0ac6f8b7 | 147 | *sdram_addr = 0xff; |
9aea9530 WD |
148 | ppcDcbf((unsigned long) sdram_addr); |
149 | udelay(100); | |
42d1f039 | 150 | |
6d0f6bcf | 151 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; |
9aea9530 | 152 | asm("sync"); |
0ac6f8b7 | 153 | *sdram_addr = 0xff; |
9aea9530 WD |
154 | ppcDcbf((unsigned long) sdram_addr); |
155 | udelay(100); | |
42d1f039 | 156 | |
6d0f6bcf | 157 | lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; |
9aea9530 | 158 | asm("sync"); |
0ac6f8b7 | 159 | *sdram_addr = 0xff; |
9aea9530 WD |
160 | ppcDcbf((unsigned long) sdram_addr); |
161 | udelay(100); | |
42d1f039 WD |
162 | } |
163 | ||
42d1f039 WD |
164 | #if !defined(CONFIG_SPD_EEPROM) |
165 | /************************************************************************* | |
166 | * fixed sdram init -- doesn't use serial presence detect. | |
167 | ************************************************************************/ | |
38dba0c2 | 168 | phys_size_t fixed_sdram(void) |
42d1f039 | 169 | { |
6d0f6bcf | 170 | #ifndef CONFIG_SYS_RAMBOOT |
9a17eb5b YS |
171 | struct ccsr_ddr __iomem *ddr = |
172 | (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); | |
6d0f6bcf JCPV |
173 | |
174 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; | |
175 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; | |
176 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; | |
177 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; | |
178 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE; | |
179 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; | |
42d1f039 WD |
180 | #if defined (CONFIG_DDR_ECC) |
181 | ddr->err_disable = 0x0000000D; | |
182 | ddr->err_sbe = 0x00ff0000; | |
183 | #endif | |
184 | asm("sync;isync;msync"); | |
185 | udelay(500); | |
186 | #if defined (CONFIG_DDR_ECC) | |
187 | /* Enable ECC checking */ | |
6d0f6bcf | 188 | ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
42d1f039 | 189 | #else |
6d0f6bcf | 190 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
42d1f039 WD |
191 | #endif |
192 | asm("sync; isync; msync"); | |
193 | udelay(500); | |
194 | #endif | |
6d0f6bcf | 195 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
42d1f039 WD |
196 | } |
197 | #endif /* !defined(CONFIG_SPD_EEPROM) */ | |
9aea9530 WD |
198 | |
199 | ||
200 | #if defined(CONFIG_PCI) | |
201 | /* | |
202 | * Initialize PCI Devices, report devices found. | |
203 | */ | |
204 | ||
9aea9530 | 205 | |
52c7a68b | 206 | static struct pci_controller hose; |
9aea9530 WD |
207 | |
208 | #endif /* CONFIG_PCI */ | |
209 | ||
210 | ||
211 | void | |
212 | pci_init_board(void) | |
213 | { | |
214 | #ifdef CONFIG_PCI | |
9aea9530 WD |
215 | pci_mpc85xx_init(&hose); |
216 | #endif /* CONFIG_PCI */ | |
217 | } | |
40d5fa35 MM |
218 | |
219 | ||
0fd5ec66 | 220 | #if defined(CONFIG_OF_BOARD_SETUP) |
e895a4b0 | 221 | int ft_board_setup(void *blob, bd_t *bd) |
40d5fa35 | 222 | { |
0fd5ec66 KG |
223 | int node, tmp[2]; |
224 | const char *path; | |
40d5fa35 MM |
225 | |
226 | ft_cpu_setup(blob, bd); | |
227 | ||
0fd5ec66 KG |
228 | node = fdt_path_offset(blob, "/aliases"); |
229 | tmp[0] = 0; | |
230 | if (node >= 0) { | |
231 | #ifdef CONFIG_PCI | |
232 | path = fdt_getprop(blob, node, "pci0", NULL); | |
233 | if (path) { | |
234 | tmp[1] = hose.last_busno - hose.first_busno; | |
235 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); | |
236 | } | |
237 | #endif | |
40d5fa35 | 238 | } |
e895a4b0 SG |
239 | |
240 | return 0; | |
40d5fa35 MM |
241 | } |
242 | #endif |