[thirdparty/u-boot.git] / board / freescale / mpc8541cds / mpc8541cds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <linux/libfdt.h>
#include <fdt_support.h>

#include "../common/cadmus.h"
#include "../common/eeprom.h"
#include "../common/via.h"

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

void local_bus_init(void);

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*            conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*            conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	char buf[32];

	/* PCI slot in USER bits CSR[6:7] by convention. */
	uint pci_slot = get_pci_slot ();

	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */

	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */

	uint cpu_board_rev = get_cpu_board_revision ();

	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
		get_board_version (), pci_slot);

	printf ("CPU Board Revision %d.%d (0x%04x)\n",
		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);

	printf("PCI1: %d bit, %s MHz, %s\n",
		(pci1_32) ? 32 : 64,
		strmhz(buf, pci1_speed),
		pci1_clk_sel ? "sync" : "async");

	if (pci_dual) {
		printf("PCI2: 32 bit, 66 MHz, %s\n",
			pci2_clk_sel ? "sync" : "async");
	} else {
		printf("PCI2: disabled\n");
	}

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;
	uint temp_lbcdll;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
	 * If localbus freq is > 133MHz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */

	} else {
		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)

	uint idx;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint cpu_board_rev;
	uint lsdmr_common;

	puts("LBC SDRAM: ");
	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
		   "\n       ");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");

	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("msync");

	/*
	 * Determine which address lines to use baed on CPU board rev.
	 */
	cpu_board_rev = get_cpu_board_revision();
	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
		lsdmr_common |= LSDMR_BSMA1617;
	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
		lsdmr_common |= LSDMR_BSMA1516;
	} else {
		/*
		 * Assume something unable to identify itself is
		 * really old, and likely has lines 16/17 mapped.
		 */
		lsdmr_common |= LSDMR_BSMA1617;
	}

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_PCI)
/* For some reason the Tundra PCI bridge shows up on itself as a
 * different device.  Work around that by refusing to configure it.
 */
void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }

static struct pci_config_table pci_mpc85xxcds_config_table[] = {
	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
		mpc85xx_config_via_usbide, {0,0,0}},
	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
		mpc85xx_config_via_usb, {0,0,0}},
	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
		mpc85xx_config_via_usb2, {0,0,0}},
	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
		mpc85xx_config_via_power, {0,0,0}},
	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
		mpc85xx_config_via_ac97, {0,0,0}},
	{},
};

static struct pci_controller hose[] = {
	{ config_table: pci_mpc85xxcds_config_table,},
#ifdef CONFIG_MPC85XX_PCI2
	{},
#endif
};

#endif	/* CONFIG_PCI */

void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(hose);
#endif
}

#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_pci_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI1
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = hose[0].last_busno - hose[0].first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
#ifdef CONFIG_MPC85XX_PCI2
		path = fdt_getprop(blob, node, "pci1", NULL);
		if (path) {
			tmp[1] = hose[1].last_busno - hose[1].first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
03f5c550	2	/*
568336ec	3	* Copyright 2004, 2011 Freescale Semiconductor.
03f5c550 WD	4	*
03f5c550 WD	5	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
03f5c550 WD	6	*/
03f5c550 WD	7
03f5c550 WD	8	#include <common.h>
	9	#include <pci.h>
	10	#include <asm/processor.h>
aa11d85c	11	#include <asm/mmu.h>
03f5c550	12	#include <asm/immap_85xx.h>
5614e71b	13	#include <fsl_ddr_sdram.h>
2d5df63e	14	#include <ioports.h>
a30a549a	15	#include <spd_sdram.h>
b08c8c48	16	#include <linux/libfdt.h>
b90d2549	17	#include <fdt_support.h>
03f5c550 WD	18
	19	#include "../common/cadmus.h"
	20	#include "../common/eeprom.h"
cbfc7ce7	21	#include "../common/via.h"
03f5c550	22
d9b94f28	23	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
03f5c550 WD	24	extern void ddr_enable_ecc(unsigned int dram_size);
	25	#endif
	26
03f5c550	27	void local_bus_init(void);
03f5c550	28
2d5df63e WD	29	/*
	30	* I/O Port configuration table
	31	*
	32	* if conf is 1, then that port pin will be configured at boot time
	33	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	34	*/
	35
	36	const iop_conf_t iop_conf_tab[4][32] = {
	37
	38	/* Port A configuration */
	39	{ /* conf ppar psor pdir podr pdat */
	40	/* PA31 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxENB */
	41	/* PA30 / { 0, 1, 0, 0, 0, 0 }, / FCC1 TxClav */
	42	/* PA29 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxSOC */
	43	/* PA28 / { 0, 1, 0, 1, 0, 0 }, / FCC1 RxENB */
	44	/* PA27 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxSOC */
	45	/* PA26 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxClav */
	46	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	47	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	48	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
	49	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
	50	/* PA21 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[4] */
	51	/* PA20 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[5] */
	52	/* PA19 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[6] */
	53	/* PA18 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[7] */
	54	/* PA17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[7] */
	55	/* PA16 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[6] */
	56	/* PA15 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[5] */
	57	/* PA14 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[4] */
	58	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
	59	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
	60	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
	61	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
	62	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
	63	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
	64	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	65	/* PA6 / { 0, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
	66	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	67	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	68	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	69	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	70	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FREERUN */
	71	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	72	},
	73
	74	/* Port B configuration */
	75	{ /* conf ppar psor pdir podr pdat */
	76	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	77	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	78	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	79	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	80	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	81	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	82	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	83	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	84	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	85	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	86	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	87	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	88	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	89	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
	90	/* PB17 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
	91	/* PB16 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
	92	/* PB15 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
93	/* PB14 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
94	/* PB13 / { 0, 1, 0, 0, 0, 0 }, / FCC3:COL */
95	/* PB12 / { 0, 1, 0, 0, 0, 0 }, / FCC3:CRS */
96	/* PB11 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
97	/* PB10 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
98	/* PB9 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
99	/* PB8 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
100	/* PB7 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
101	/* PB6 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
102	/* PB5 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
103	/* PB4 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
104	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
105	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
106	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
107	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
108	},
109
110	/* Port C */
111	{ /* conf ppar psor pdir podr pdat */
112	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
113	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
114	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
115	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
116	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
117	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
118	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
119	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
120	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
121	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
122	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
123	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
124	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
125	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
126	/* PC17 / { 0, 0, 0, 1, 0, 0 }, / PC17 */
127	/* PC16 / { 0, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
128	/* PC15 / { 1, 1, 0, 0, 0, 0 }, / PC15 */
129	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
130	/* PC13 / { 0, 0, 0, 1, 0, 0 }, / PC13 */
131	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
132	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
133	/* PC10 / { 1, 0, 0, 1, 0, 0 }, / FETHMDC */
134	/* PC9 / { 1, 0, 0, 0, 0, 0 }, / FETHMDIO */
135	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
136	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
137	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
138	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
139	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
140	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
141	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
142	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
143	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
144	},
145
146	/* Port D */
147	{ /* conf ppar psor pdir podr pdat */
148	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
149	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
150	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
151	/* PD28 / { 0, 1, 0, 0, 0, 0 }, / PD28 */
152	/* PD27 / { 0, 1, 1, 1, 0, 0 }, / PD27 */
153	/* PD26 / { 0, 0, 0, 1, 0, 0 }, / PD26 */
154	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
155	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
156	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
157	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
158	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
159	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
160	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
161	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
162	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
163	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
164	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
165	/* PD14 / { 0, 0, 0, 1, 0, 0 }, / LED */
166	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
167	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
168	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
169	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
170	/* PD9 / { 0, 1, 0, 1, 0, 0 }, / SMC1 TXD */
171	/* PD8 / { 0, 1, 0, 0, 0, 0 }, / SMC1 RXD */
172	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
173	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
174	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
175	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
176	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
177	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
178	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
179	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
180	}
181	};
182
5c952cf0	183	int checkboard (void)
03f5c550	184	{
6d0f6bcf	185	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
568336ec	186	char buf[32];
5c952cf0 WD	187
	188	/* PCI slot in USER bits CSR[6:7] by convention. */
	189	uint pci_slot = get_pci_slot ();
03f5c550	190
5c952cf0 WD	191	uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
	192	uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
	193	uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
	194	uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
	195
	196	uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
	197
	198	uint cpu_board_rev = get_cpu_board_revision ();
	199
	200	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
	201	get_board_version (), pci_slot);
	202
	203	printf ("CPU Board Revision %d.%d (0x%04x)\n",
	204	MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
	205	MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
	206
8ca78f2c	207	printf("PCI1: %d bit, %s MHz, %s\n",
5c952cf0	208	(pci1_32) ? 32 : 64,
568336ec	209	strmhz(buf, pci1_speed),
5c952cf0 WD	210	pci1_clk_sel ? "sync" : "async");
	211
	212	if (pci_dual) {
8ca78f2c	213	printf("PCI2: 32 bit, 66 MHz, %s\n",
5c952cf0 WD	214	pci2_clk_sel ? "sync" : "async");
5c952cf0 WD	215	} else {
8ca78f2c	216	printf("PCI2: disabled\n");
5c952cf0 WD	217	}
	218
	219	/*
	220	* Initialize local bus.
	221	*/
	222	local_bus_init ();
	223
	224	return 0;
	225	}
03f5c550	226
03f5c550 WD	227	/*
	228	* Initialize Local Bus
	229	*/
03f5c550 WD	230	void
	231	local_bus_init(void)
	232	{
6d0f6bcf	233	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	234	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
03f5c550 WD	235
	236	uint clkdiv;
	237	uint lbc_hz;
	238	sys_info_t sysinfo;
	239	uint temp_lbcdll;
	240
	241	/*
	242	* Errata LBC11.
	243	* Fix Local Bus clock glitch when DLL is enabled.
	244	*
8ed44d91 WD	245	* If localbus freq is < 66MHz, DLL bypass mode must be used.
8ed44d91 WD	246	* If localbus freq is > 133MHz, DLL can be safely enabled.
03f5c550 WD	247	* Between 66 and 133, the DLL is enabled with an override workaround.
	248	*/
	249
	250	get_sys_info(&sysinfo);
a5d212a2	251	clkdiv = lbc->lcrr & LCRR_CLKDIV;
997399fa	252	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
03f5c550 WD	253
03f5c550 WD	254	if (lbc_hz < 66) {
a2af6a7a	255	lbc->lcrr \|= LCRR_DBYP; /* DLL Bypass */
03f5c550 WD	256
03f5c550 WD	257	} else if (lbc_hz >= 133) {
a2af6a7a	258	lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
03f5c550 WD	259
03f5c550 WD	260	} else {
a2af6a7a	261	lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
03f5c550 WD	262	udelay(200);
	263
	264	/*
	265	* Sample LBC DLL ctrl reg, upshift it to set the
	266	* override bits.
	267	*/
	268	temp_lbcdll = gur->lbcdllcr;
	269	gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) \| 0x80000000);
	270	asm("sync;isync;msync");
	271	}
	272	}
	273
03f5c550 WD	274	/*
	275	* Initialize SDRAM memory on the Local Bus.
	276	*/
70961ba4	277	void lbc_sdram_init(void)
03f5c550	278	{
6d0f6bcf	279	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
03f5c550 WD	280
03f5c550 WD	281	uint idx;
f51cdaf1	282	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	283	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
03f5c550 WD	284	uint cpu_board_rev;
	285	uint lsdmr_common;
	286
7ea3871e BB	287	puts("LBC SDRAM: ");
	288	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
	289	"\n ");
03f5c550 WD	290
	291	/*
	292	* Setup SDRAM Base and Option Registers
	293	*/
f51cdaf1 BB	294	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
f51cdaf1 BB	295	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
6d0f6bcf	296	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
03f5c550 WD	297	asm("msync");
03f5c550 WD	298
6d0f6bcf JCPV	299	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	300	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
03f5c550 WD	301	asm("msync");
	302
	303	/*
	304	* Determine which address lines to use baed on CPU board rev.
	305	*/
	306	cpu_board_rev = get_cpu_board_revision();
6d0f6bcf	307	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
03f5c550	308	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
b0fe93ed	309	lsdmr_common \|= LSDMR_BSMA1617;
03f5c550	310	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
b0fe93ed	311	lsdmr_common \|= LSDMR_BSMA1516;
03f5c550 WD	312	} else {
	313	/*
	314	* Assume something unable to identify itself is
	315	* really old, and likely has lines 16/17 mapped.
	316	*/
b0fe93ed	317	lsdmr_common \|= LSDMR_BSMA1617;
03f5c550 WD	318	}
	319
	320	/*
	321	* Issue PRECHARGE ALL command.
	322	*/
b0fe93ed	323	lbc->lsdmr = lsdmr_common \| LSDMR_OP_PCHALL;
03f5c550 WD	324	asm("sync;msync");
	325	*sdram_addr = 0xff;
	326	ppcDcbf((unsigned long) sdram_addr);
	327	udelay(100);
	328
	329	/*
	330	* Issue 8 AUTO REFRESH commands.
	331	*/
	332	for (idx = 0; idx < 8; idx++) {
b0fe93ed	333	lbc->lsdmr = lsdmr_common \| LSDMR_OP_ARFRSH;
03f5c550 WD	334	asm("sync;msync");
	335	*sdram_addr = 0xff;
	336	ppcDcbf((unsigned long) sdram_addr);
	337	udelay(100);
	338	}
	339
	340	/*
	341	* Issue 8 MODE-set command.
	342	*/
b0fe93ed	343	lbc->lsdmr = lsdmr_common \| LSDMR_OP_MRW;
03f5c550 WD	344	asm("sync;msync");
	345	*sdram_addr = 0xff;
	346	ppcDcbf((unsigned long) sdram_addr);
	347	udelay(100);
	348
	349	/*
	350	* Issue NORMAL OP command.
	351	*/
b0fe93ed	352	lbc->lsdmr = lsdmr_common \| LSDMR_OP_NORMAL;
03f5c550 WD	353	asm("sync;msync");
	354	*sdram_addr = 0xff;
	355	ppcDcbf((unsigned long) sdram_addr);
	356	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	357
	358	#endif /* enable SDRAM init */
	359	}
	360
03f5c550	361	#if defined(CONFIG_PCI)
cbfc7ce7 MM	362	/* For some reason the Tundra PCI bridge shows up on itself as a
cbfc7ce7 MM	363	* different device. Work around that by refusing to configure it.
03f5c550	364	*/
cbfc7ce7	365	void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
03f5c550	366
03f5c550	367	static struct pci_config_table pci_mpc85xxcds_config_table[] = {
cbfc7ce7	368	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
7f3f2bd2 RV	369	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
7f3f2bd2 RV	370	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
ffa621a0	371	mpc85xx_config_via_usbide, {0,0,0}},
7f3f2bd2 RV	372	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
	373	mpc85xx_config_via_usb, {0,0,0}},
	374	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
	375	mpc85xx_config_via_usb2, {0,0,0}},
	376	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
ffa621a0	377	mpc85xx_config_via_power, {0,0,0}},
7f3f2bd2 RV	378	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
7f3f2bd2 RV	379	mpc85xx_config_via_ac97, {0,0,0}},
ffa621a0	380	{},
03f5c550	381	};
03f5c550	382
cbfc7ce7 MM	383	static struct pci_controller hose[] = {
	384	{ config_table: pci_mpc85xxcds_config_table,},
	385	#ifdef CONFIG_MPC85XX_PCI2
	386	{},
03f5c550 WD	387	#endif
	388	};
	389
	390	#endif /* CONFIG_PCI */
	391
03f5c550 WD	392	void
	393	pci_init_board(void)
	394	{
	395	#ifdef CONFIG_PCI
7376eb87	396	pci_mpc85xx_init(hose);
03f5c550 WD	397	#endif
03f5c550 WD	398	}
b90d2549 KG	399
	400	#if defined(CONFIG_OF_BOARD_SETUP)
	401	void
	402	ft_pci_setup(void blob, bd_t bd)
	403	{
	404	int node, tmp[2];
	405	const char *path;
	406
	407	node = fdt_path_offset(blob, "/aliases");
	408	tmp[0] = 0;
	409	if (node >= 0) {
	410	#ifdef CONFIG_PCI1
	411	path = fdt_getprop(blob, node, "pci0", NULL);
	412	if (path) {
	413	tmp[1] = hose[0].last_busno - hose[0].first_busno;
	414	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	415	}
	416	#endif
	417	#ifdef CONFIG_MPC85XX_PCI2
	418	path = fdt_getprop(blob, node, "pci1", NULL);
	419	if (path) {
	420	tmp[1] = hose[1].last_busno - hose[1].first_busno;
	421	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	422	}
	423	#endif
	424	}
	425	}
	426	#endif