[people/ms/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

/*
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/pixis.h"
#include "../common/sgmii_riser.h"

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: MPC8544DS, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
		in8(PIXIS_BASE + PIXIS_PVER));

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);

	dram_size *= 0x100000;

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	puts("    DDR: ");
	return dram_size;
}

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
		devdisr, io_sel, host_agent);

	if (io_sel & 1) {
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
			printf ("    eTSEC1 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
			printf ("    eTSEC3 is in sgmii mode.\n");
	}

#ifdef CONFIG_PCIE3
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
	struct pci_controller *hose = &pcie3_hose;
	int pcie_ep = (host_agent == 1);
	int pcie_configured  = io_sel >= 1;
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BASE,
			       CONFIG_SYS_PCIE3_MEM_PHYS,
			       CONFIG_SYS_PCIE3_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_IO_BASE,
			       CONFIG_SYS_PCIE3_IO_PHYS,
			       CONFIG_SYS_PCIE3_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BASE2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf ("    PCIE3 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
	} else {
		printf ("    PCIE3: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep = (host_agent == 5);
	int pcie_configured  = io_sel & 6;
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BASE,
			       CONFIG_SYS_PCIE1_MEM_PHYS,
			       CONFIG_SYS_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_IO_BASE,
			       CONFIG_SYS_PCIE1_IO_PHYS,
			       CONFIG_SYS_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BASE2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
		       hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE1: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

#ifdef CONFIG_PCIE2
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
	struct pci_controller *hose = &pcie2_hose;
	int pcie_ep = (host_agent == 3);
	int pcie_configured  = io_sel & 4;
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_MEM_BASE,
			       CONFIG_SYS_PCIE2_MEM_PHYS,
			       CONFIG_SYS_PCIE2_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_IO_BASE,
			       CONFIG_SYS_PCIE2_IO_PHYS,
			       CONFIG_SYS_PCIE2_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE2_MEM_BASE2,
			       CONFIG_SYS_PCIE2_MEM_PHYS2,
			       CONFIG_SYS_PCIE2_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("    PCIE2 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE2: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif


#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	struct pci_region *r = hose->regions;

	uint pci_agent = (host_agent == 6);
	uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
	uint pci_32 = 1;
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */


	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			(uint)pci
			);

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_MEM_BASE,
			       CONFIG_SYS_PCI1_MEM_PHYS,
			       CONFIG_SYS_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_IO_BASE,
			       CONFIG_SYS_PCI1_IO_PHYS,
			       CONFIG_SYS_PCI1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE3_MEM_BASE2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
}


int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;

	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in8(PIXIS_BASE + PIXIS_AUX);
		else
			i = in8(PIXIS_BASE + PIXIS_SPD);
	} else {
		i = in8(PIXIS_BASE + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct tsec_info_struct tsec_info[2];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	if (io_sel & 1)
		fsl_sgmii_riser_init(tsec_info, num);


	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
                        struct pci_controller *hose);

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);


#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE3
	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
}
#endif
Commit	Line	Data
25d83d7f JL	1	/*
	2	* Copyright 2007 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
837f1ba0	25	#include <pci.h>
25d83d7f	26	#include <asm/processor.h>
1167a2fd	27	#include <asm/mmu.h>
25d83d7f	28	#include <asm/immap_85xx.h>
837f1ba0	29	#include <asm/immap_fsl_pci.h>
1167a2fd	30	#include <asm/fsl_ddr_sdram.h>
56a92705	31	#include <asm/io.h>
25d83d7f	32	#include <miiphy.h>
addce57e KG	33	#include <libfdt.h>
addce57e KG	34	#include <fdt_support.h>
216f2a71	35	#include <tsec.h>
0b252f50	36	#include <netdev.h>
25d83d7f JL	37
25d83d7f JL	38	#include "../common/pixis.h"
216f2a71	39	#include "../common/sgmii_riser.h"
25d83d7f	40
25d83d7f JL	41	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	42	extern void ddr_enable_ecc(unsigned int dram_size);
	43	#endif
	44
25d83d7f JL	45	int checkboard (void)
25d83d7f JL	46	{
6d0f6bcf JCPV	47	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	48	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	49	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
25d83d7f	50
2f15278c	51	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	52	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
25d83d7f	53	}
e5852787 KG	54	printf ("Board: MPC8544DS, System ID: 0x%02x, "
	55	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
	56	in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
	57	in8(PIXIS_BASE + PIXIS_PVER));
25d83d7f	58
837f1ba0 ES	59	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	60	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	61	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	62	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	63
25d83d7f JL	64	return 0;
	65	}
	66
9973e3c6	67	phys_size_t
25d83d7f JL	68	initdram(int board_type)
	69	{
	70	long dram_size = 0;
	71
	72	puts("Initializing\n");
	73
1167a2fd KG	74	dram_size = fsl_ddr_sdram();
	75
	76	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	77
	78	dram_size *= 0x100000;
25d83d7f JL	79
	80	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	81	/*
	82	* Initialize and enable DDR ECC.
	83	*/
	84	ddr_enable_ecc(dram_size);
	85	#endif
	86	puts(" DDR: ");
	87	return dram_size;
	88	}
	89
837f1ba0 ES	90	#ifdef CONFIG_PCI1
	91	static struct pci_controller pci1_hose;
	92	#endif
	93
	94	#ifdef CONFIG_PCIE1
	95	static struct pci_controller pcie1_hose;
	96	#endif
	97
	98	#ifdef CONFIG_PCIE2
	99	static struct pci_controller pcie2_hose;
	100	#endif
	101
	102	#ifdef CONFIG_PCIE3
	103	static struct pci_controller pcie3_hose;
	104	#endif
	105
2dba0dea KG	106	extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
	107	extern void fsl_pci_init(struct pci_controller *hose);
	108
837f1ba0 ES	109	int first_free_busno=0;
	110
	111	void
	112	pci_init_board(void)
	113	{
6d0f6bcf	114	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
837f1ba0 ES	115	uint devdisr = gur->devdisr;
	116	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	117	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	118
	119	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	120	devdisr, io_sel, host_agent);
	121
	122	if (io_sel & 1) {
	123	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	124	printf (" eTSEC1 is in sgmii mode.\n");
	125	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	126	printf (" eTSEC3 is in sgmii mode.\n");
	127	}
	128
	129	#ifdef CONFIG_PCIE3
	130	{
6d0f6bcf	131	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE3_ADDR;
837f1ba0	132	struct pci_controller *hose = &pcie3_hose;
f97abbfb	133	int pcie_ep = (host_agent == 1);
837f1ba0	134	int pcie_configured = io_sel >= 1;
2dba0dea	135	struct pci_region *r = hose->regions;
837f1ba0 ES	136
	137	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	138	printf ("\n PCIE3 connected to ULI as %s (base address %x)",
	139	pcie_ep ? "End Point" : "Root Complex",
	140	(uint)pci);
	141	if (pci->pme_msg_det) {
	142	pci->pme_msg_det = 0xffffffff;
	143	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	144	}
	145	printf ("\n");
	146
	147	/* inbound */
2dba0dea	148	r += fsl_pci_setup_inbound_windows(r);
837f1ba0 ES	149
837f1ba0 ES	150	/* outbound memory */
2dba0dea	151	pci_set_region(r++,
6d0f6bcf JCPV	152	CONFIG_SYS_PCIE3_MEM_BASE,
	153	CONFIG_SYS_PCIE3_MEM_PHYS,
	154	CONFIG_SYS_PCIE3_MEM_SIZE,
837f1ba0 ES	155	PCI_REGION_MEM);
	156
	157	/* outbound io */
2dba0dea	158	pci_set_region(r++,
6d0f6bcf JCPV	159	CONFIG_SYS_PCIE3_IO_BASE,
	160	CONFIG_SYS_PCIE3_IO_PHYS,
	161	CONFIG_SYS_PCIE3_IO_SIZE,
837f1ba0 ES	162	PCI_REGION_IO);
837f1ba0 ES	163
6d0f6bcf	164	#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
837f1ba0	165	/* outbound memory */
2dba0dea	166	pci_set_region(r++,
6d0f6bcf JCPV	167	CONFIG_SYS_PCIE3_MEM_BASE2,
	168	CONFIG_SYS_PCIE3_MEM_PHYS2,
	169	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	170	PCI_REGION_MEM);
837f1ba0	171	#endif
2dba0dea	172	hose->region_count = r - hose->regions;
837f1ba0 ES	173	hose->first_busno=first_free_busno;
	174	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	175
	176	fsl_pci_init(hose);
	177
	178	first_free_busno=hose->last_busno+1;
	179	printf (" PCIE3 on bus %02x - %02x\n",
	180	hose->first_busno,hose->last_busno);
	181
56a92705 KG	182	/*
	183	* Activate ULI1575 legacy chip by performing a fake
	184	* memory access. Needed to make ULI RTC work.
	185	*/
6d0f6bcf	186	in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
837f1ba0 ES	187	} else {
	188	printf (" PCIE3: disabled\n");
	189	}
	190
	191	}
	192	#else
	193	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
	194	#endif
	195
	196	#ifdef CONFIG_PCIE1
	197	{
6d0f6bcf	198	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
837f1ba0 ES	199	struct pci_controller *hose = &pcie1_hose;
	200	int pcie_ep = (host_agent == 5);
	201	int pcie_configured = io_sel & 6;
2dba0dea	202	struct pci_region *r = hose->regions;
837f1ba0 ES	203
	204	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	205	printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
	206	pcie_ep ? "End Point" : "Root Complex",
	207	(uint)pci);
	208	if (pci->pme_msg_det) {
	209	pci->pme_msg_det = 0xffffffff;
	210	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	211	}
	212	printf ("\n");
	213
	214	/* inbound */
2dba0dea	215	r += fsl_pci_setup_inbound_windows(r);
837f1ba0 ES	216
837f1ba0 ES	217	/* outbound memory */
2dba0dea	218	pci_set_region(r++,
6d0f6bcf JCPV	219	CONFIG_SYS_PCIE1_MEM_BASE,
	220	CONFIG_SYS_PCIE1_MEM_PHYS,
	221	CONFIG_SYS_PCIE1_MEM_SIZE,
837f1ba0 ES	222	PCI_REGION_MEM);
	223
	224	/* outbound io */
2dba0dea	225	pci_set_region(r++,
6d0f6bcf JCPV	226	CONFIG_SYS_PCIE1_IO_BASE,
	227	CONFIG_SYS_PCIE1_IO_PHYS,
	228	CONFIG_SYS_PCIE1_IO_SIZE,
837f1ba0 ES	229	PCI_REGION_IO);
837f1ba0 ES	230
6d0f6bcf	231	#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
837f1ba0	232	/* outbound memory */
2dba0dea	233	pci_set_region(r++,
6d0f6bcf JCPV	234	CONFIG_SYS_PCIE1_MEM_BASE2,
	235	CONFIG_SYS_PCIE1_MEM_PHYS2,
	236	CONFIG_SYS_PCIE1_MEM_SIZE2,
837f1ba0	237	PCI_REGION_MEM);
837f1ba0	238	#endif
2dba0dea	239	hose->region_count = r - hose->regions;
837f1ba0 ES	240	hose->first_busno=first_free_busno;
	241
	242	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	243
	244	fsl_pci_init(hose);
	245
	246	first_free_busno=hose->last_busno+1;
	247	printf(" PCIE1 on bus %02x - %02x\n",
	248	hose->first_busno,hose->last_busno);
	249
	250	} else {
	251	printf (" PCIE1: disabled\n");
	252	}
	253
	254	}
	255	#else
	256	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	257	#endif
	258
	259	#ifdef CONFIG_PCIE2
	260	{
6d0f6bcf	261	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE2_ADDR;
837f1ba0 ES	262	struct pci_controller *hose = &pcie2_hose;
	263	int pcie_ep = (host_agent == 3);
	264	int pcie_configured = io_sel & 4;
2dba0dea	265	struct pci_region *r = hose->regions;
837f1ba0 ES	266
	267	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	268	printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
	269	pcie_ep ? "End Point" : "Root Complex",
	270	(uint)pci);
	271	if (pci->pme_msg_det) {
	272	pci->pme_msg_det = 0xffffffff;
	273	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	274	}
	275	printf ("\n");
	276
	277	/* inbound */
2dba0dea	278	r += fsl_pci_setup_inbound_windows(r);
837f1ba0 ES	279
837f1ba0 ES	280	/* outbound memory */
2dba0dea	281	pci_set_region(r++,
6d0f6bcf JCPV	282	CONFIG_SYS_PCIE2_MEM_BASE,
	283	CONFIG_SYS_PCIE2_MEM_PHYS,
	284	CONFIG_SYS_PCIE2_MEM_SIZE,
837f1ba0 ES	285	PCI_REGION_MEM);
	286
	287	/* outbound io */
2dba0dea	288	pci_set_region(r++,
6d0f6bcf JCPV	289	CONFIG_SYS_PCIE2_IO_BASE,
	290	CONFIG_SYS_PCIE2_IO_PHYS,
	291	CONFIG_SYS_PCIE2_IO_SIZE,
837f1ba0 ES	292	PCI_REGION_IO);
837f1ba0 ES	293
6d0f6bcf	294	#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
837f1ba0	295	/* outbound memory */
2dba0dea	296	pci_set_region(r++,
6d0f6bcf JCPV	297	CONFIG_SYS_PCIE2_MEM_BASE2,
	298	CONFIG_SYS_PCIE2_MEM_PHYS2,
	299	CONFIG_SYS_PCIE2_MEM_SIZE2,
837f1ba0	300	PCI_REGION_MEM);
837f1ba0	301	#endif
2dba0dea	302	hose->region_count = r - hose->regions;
837f1ba0 ES	303	hose->first_busno=first_free_busno;
	304	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	305
	306	fsl_pci_init(hose);
	307	first_free_busno=hose->last_busno+1;
	308	printf (" PCIE2 on bus %02x - %02x\n",
	309	hose->first_busno,hose->last_busno);
	310
	311	} else {
	312	printf (" PCIE2: disabled\n");
	313	}
	314
	315	}
	316	#else
	317	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
	318	#endif
	319
	320
	321	#ifdef CONFIG_PCI1
	322	{
6d0f6bcf	323	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
837f1ba0	324	struct pci_controller *hose = &pci1_hose;
2dba0dea	325	struct pci_region *r = hose->regions;
837f1ba0 ES	326
	327	uint pci_agent = (host_agent == 6);
	328	uint pci_speed = 66666000; /get_clock_freq (); PCI PSPEED in [4:5] /
	329	uint pci_32 = 1;
	330	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	331	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	332
	333
	334	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	335	printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
	336	(pci_32) ? 32 : 64,
	337	(pci_speed == 33333000) ? "33" :
	338	(pci_speed == 66666000) ? "66" : "unknown",
	339	pci_clk_sel ? "sync" : "async",
	340	pci_agent ? "agent" : "host",
	341	pci_arb ? "arbiter" : "external-arbiter",
	342	(uint)pci
	343	);
	344
	345	/* inbound */
2dba0dea	346	r += fsl_pci_setup_inbound_windows(r);
837f1ba0 ES	347
837f1ba0 ES	348	/* outbound memory */
2dba0dea	349	pci_set_region(r++,
6d0f6bcf JCPV	350	CONFIG_SYS_PCI1_MEM_BASE,
	351	CONFIG_SYS_PCI1_MEM_PHYS,
	352	CONFIG_SYS_PCI1_MEM_SIZE,
837f1ba0 ES	353	PCI_REGION_MEM);
	354
	355	/* outbound io */
2dba0dea	356	pci_set_region(r++,
6d0f6bcf JCPV	357	CONFIG_SYS_PCI1_IO_BASE,
	358	CONFIG_SYS_PCI1_IO_PHYS,
	359	CONFIG_SYS_PCI1_IO_SIZE,
837f1ba0	360	PCI_REGION_IO);
2dba0dea	361
6d0f6bcf	362	#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
837f1ba0	363	/* outbound memory */
2dba0dea	364	pci_set_region(r++,
6d0f6bcf JCPV	365	CONFIG_SYS_PCIE3_MEM_BASE2,
	366	CONFIG_SYS_PCIE3_MEM_PHYS2,
	367	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	368	PCI_REGION_MEM);
837f1ba0	369	#endif
2dba0dea	370	hose->region_count = r - hose->regions;
837f1ba0 ES	371	hose->first_busno=first_free_busno;
	372	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	373
	374	fsl_pci_init(hose);
	375	first_free_busno=hose->last_busno+1;
	376	printf ("PCI on bus %02x - %02x\n",
	377	hose->first_busno,hose->last_busno);
	378	} else {
	379	printf (" PCI: disabled\n");
	380	}
	381	}
	382	#else
	383	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	384	#endif
	385	}
	386
	387
25d83d7f JL	388	int last_stage_init(void)
	389	{
	390	return 0;
	391	}
	392
	393
	394	unsigned long
	395	get_board_sys_clk(ulong dummy)
	396	{
	397	u8 i, go_bit, rd_clks;
	398	ulong val = 0;
	399
	400	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	401	go_bit &= 0x01;
	402
	403	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	404	rd_clks &= 0x1C;
	405
	406	/*
	407	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	408	* should we be using the AUX register. Remember, we also set the
	409	* GO bit to boot from the alternate bank on the on-board flash
	410	*/
	411
	412	if (go_bit) {
	413	if (rd_clks == 0x1c)
	414	i = in8(PIXIS_BASE + PIXIS_AUX);
	415	else
	416	i = in8(PIXIS_BASE + PIXIS_SPD);
	417	} else {
	418	i = in8(PIXIS_BASE + PIXIS_SPD);
	419	}
	420
	421	i &= 0x07;
	422
	423	switch (i) {
	424	case 0:
	425	val = 33333333;
	426	break;
	427	case 1:
	428	val = 40000000;
	429	break;
	430	case 2:
	431	val = 50000000;
	432	break;
	433	case 3:
	434	val = 66666666;
	435	break;
	436	case 4:
	437	val = 83000000;
	438	break;
	439	case 5:
	440	val = 100000000;
	441	break;
	442	case 6:
	443	val = 133333333;
	444	break;
	445	case 7:
	446	val = 166666666;
	447	break;
	448	}
	449
	450	return val;
	451	}
452
216f2a71 AF	453	int board_eth_init(bd_t *bis)
216f2a71 AF	454	{
0b252f50	455	#ifdef CONFIG_TSEC_ENET
216f2a71	456	struct tsec_info_struct tsec_info[2];
6d0f6bcf	457	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
216f2a71 AF	458	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	459	int num = 0;
	460
	461	#ifdef CONFIG_TSEC1
	462	SET_STD_TSEC_INFO(tsec_info[num], 1);
	463	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	464	tsec_info[num].flags \|= TSEC_SGMII;
	465	num++;
	466	#endif
	467	#ifdef CONFIG_TSEC3
	468	SET_STD_TSEC_INFO(tsec_info[num], 3);
	469	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	470	tsec_info[num].flags \|= TSEC_SGMII;
	471	num++;
	472	#endif
	473
	474	if (!num) {
	475	printf("No TSECs initialized\n");
	476
	477	return 0;
	478	}
	479
	480	if (io_sel & 1)
	481	fsl_sgmii_riser_init(tsec_info, num);
	482
	483
	484	tsec_eth_init(bis, tsec_info, num);
216f2a71	485	#endif
0b252f50 BW	486	return pci_eth_init(bis);
0b252f50 BW	487	}
216f2a71	488
addce57e	489	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea KG	490	extern void ft_fsl_pci_setup(void blob, const char pci_alias,
2dba0dea KG	491	struct pci_controller *hose);
addce57e	492
2dba0dea	493	void ft_board_setup(void blob, bd_t bd)
25d83d7f	494	{
2f15278c	495	ft_cpu_setup(blob, bd);
25d83d7f	496
2dba0dea	497
f75e89e9	498	#ifdef CONFIG_PCI1
2dba0dea	499	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
837f1ba0 ES	500	#endif
837f1ba0 ES	501	#ifdef CONFIG_PCIE2
2dba0dea	502	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
addce57e KG	503	#endif
addce57e KG	504	#ifdef CONFIG_PCIE1
2dba0dea	505	ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
837f1ba0 ES	506	#endif
837f1ba0 ES	507	#ifdef CONFIG_PCIE3
2dba0dea	508	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
837f1ba0	509	#endif
25d83d7f JL	510	}
25d83d7f JL	511	#endif