[people/ms/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

/*
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/io.h>
#include <spd.h>
#include <miiphy.h>

#include "../common/pixis.h"

#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

extern long int spd_sdram(void);

void sdram_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %x\n",&gur->porpllsr);
	}
	printf ("Board: MPC8544DS\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

long int
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

	dram_size = spd_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	puts("    DDR: ");
	return dram_size;
}

#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CFG_MEMTEST_START,
	       CFG_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
		devdisr, io_sel, host_agent);

	if (io_sel & 1) {
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
			printf ("    eTSEC1 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
			printf ("    eTSEC3 is in sgmii mode.\n");
	}

#ifdef CONFIG_PCIE3
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie3_hose;
	int pcie_ep = (host_agent == 3);
	int pcie_configured  = io_sel >= 1;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCIE3_MEM_BASE,
			       CFG_PCIE3_MEM_PHYS,
			       CFG_PCIE3_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCIE3_IO_BASE,
			       CFG_PCIE3_IO_PHYS,
			       CFG_PCIE3_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;
#ifdef CFG_PCIE3_MEM_BASE2
		/* outbound memory */
		pci_set_region(hose->regions + 3,
			       CFG_PCIE3_MEM_BASE2,
			       CFG_PCIE3_MEM_PHYS2,
			       CFG_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);
		hose->region_count++;
#endif
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf ("    PCIE3 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32(CFG_PCIE3_MEM_BASE);
	} else {
		printf ("    PCIE3: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep = (host_agent == 5);
	int pcie_configured  = io_sel & 6;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCIE1_MEM_BASE,
			       CFG_PCIE1_MEM_PHYS,
			       CFG_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCIE1_IO_BASE,
			       CFG_PCIE1_IO_PHYS,
			       CFG_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;
#ifdef CFG_PCIE1_MEM_BASE2
		/* outbound memory */
		pci_set_region(hose->regions + 3,
			       CFG_PCIE1_MEM_BASE2,
			       CFG_PCIE1_MEM_PHYS2,
			       CFG_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);
		hose->region_count++;
#endif
		hose->first_busno=first_free_busno;

		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
		       hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE1: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

#ifdef CONFIG_PCIE2
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie2_hose;
	int pcie_ep = (host_agent == 3);
	int pcie_configured  = io_sel & 4;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCIE2_MEM_BASE,
			       CFG_PCIE2_MEM_PHYS,
			       CFG_PCIE2_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCIE2_IO_BASE,
			       CFG_PCIE2_IO_PHYS,
			       CFG_PCIE2_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;
#ifdef CFG_PCIE2_MEM_BASE2
		/* outbound memory */
		pci_set_region(hose->regions + 3,
			       CFG_PCIE2_MEM_BASE2,
			       CFG_PCIE2_MEM_PHYS2,
			       CFG_PCIE2_MEM_SIZE2,
			       PCI_REGION_MEM);
		hose->region_count++;
#endif
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("    PCIE2 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE2: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif


#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;

	uint pci_agent = (host_agent == 6);
	uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
	uint pci_32 = 1;
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */


	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			(uint)pci
			);

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCI1_MEM_BASE,
			       CFG_PCI1_MEM_PHYS,
			       CFG_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCI1_IO_BASE,
			       CFG_PCI1_IO_PHYS,
			       CFG_PCI1_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = 3;
#ifdef CFG_PCIE3_MEM_BASE2
		/* outbound memory */
		pci_set_region(hose->regions + 3,
			       CFG_PCIE3_MEM_BASE2,
			       CFG_PCIE3_MEM_PHYS2,
			       CFG_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);
		hose->region_count++;
#endif
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
}


int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;

	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in8(PIXIS_BASE + PIXIS_AUX);
		else
			i = in8(PIXIS_BASE + PIXIS_SPD);
	} else {
		i = in8(PIXIS_BASE + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}

#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	u32 *p;
	int len;

	ft_cpu_setup(blob, bd);

	p = ft_get_prop(blob, "/memory/reg", &len);
	if (p != NULL) {
		*p++ = cpu_to_be32(bd->bi_memstart);
		*p = cpu_to_be32(bd->bi_memsize);
	}
#ifdef CONFIG_PCI1
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
	if (p != NULL) {
		p[0] = 0;
		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	}
#endif
#ifdef CONFIG_PCIE1
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
	if (p != NULL) {
		p[0] = 0;
		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	}
#endif
#ifdef CONFIG_PCIE2
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
	if (p != NULL) {
		p[0] = 0;
		p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
		debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	}
#endif
#ifdef CONFIG_PCIE3
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
	if (p != NULL) {
		p[0] = 0;
		p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
		debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	}
#endif
}
#endif
Commit	Line	Data
25d83d7f JL	1	/*
	2	* Copyright 2007 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
837f1ba0	25	#include <pci.h>
25d83d7f JL	26	#include <asm/processor.h>
25d83d7f JL	27	#include <asm/immap_85xx.h>
837f1ba0	28	#include <asm/immap_fsl_pci.h>
56a92705	29	#include <asm/io.h>
25d83d7f JL	30	#include <spd.h>
	31	#include <miiphy.h>
	32
	33	#include "../common/pixis.h"
	34
	35	#if defined(CONFIG_OF_FLAT_TREE)
	36	#include <ft_build.h>
	37	extern void ft_cpu_setup(void blob, bd_t bd);
	38	#endif
	39
	40	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	41	extern void ddr_enable_ecc(unsigned int dram_size);
	42	#endif
	43
	44	extern long int spd_sdram(void);
	45
	46	void sdram_init(void);
	47
	48	int board_early_init_f (void)
	49	{
	50	return 0;
	51	}
	52
	53	int checkboard (void)
	54	{
	55	volatile immap_t immap = (immap_t ) CFG_CCSRBAR;
	56	volatile ccsr_gur_t *gur = &immap->im_gur;
837f1ba0 ES	57	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
837f1ba0 ES	58	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
25d83d7f	59
2f15278c	60	if ((uint)&gur->porpllsr != 0xe00e0000) {
25d83d7f JL	61	printf("immap size error %x\n",&gur->porpllsr);
	62	}
	63	printf ("Board: MPC8544DS\n");
	64
837f1ba0 ES	65	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	66	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	67	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	68	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	69
25d83d7f JL	70	return 0;
	71	}
	72
	73	long int
	74	initdram(int board_type)
	75	{
	76	long dram_size = 0;
	77
	78	puts("Initializing\n");
	79
	80	dram_size = spd_sdram();
	81
	82	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	83	/*
	84	* Initialize and enable DDR ECC.
	85	*/
	86	ddr_enable_ecc(dram_size);
	87	#endif
	88	puts(" DDR: ");
	89	return dram_size;
	90	}
	91
25d83d7f JL	92	#if defined(CFG_DRAM_TEST)
	93	int
	94	testdram(void)
	95	{
	96	uint pstart = (uint ) CFG_MEMTEST_START;
	97	uint pend = (uint ) CFG_MEMTEST_END;
	98	uint *p;
	99
	100	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	101	CFG_MEMTEST_START,
	102	CFG_MEMTEST_END);
	103
	104	printf("DRAM test phase 1:\n");
	105	for (p = pstart; p < pend; p++)
	106	*p = 0xaaaaaaaa;
	107
	108	for (p = pstart; p < pend; p++) {
	109	if (*p != 0xaaaaaaaa) {
	110	printf ("DRAM test fails at: %08x\n", (uint) p);
	111	return 1;
	112	}
	113	}
	114
	115	printf("DRAM test phase 2:\n");
	116	for (p = pstart; p < pend; p++)
	117	*p = 0x55555555;
	118
	119	for (p = pstart; p < pend; p++) {
	120	if (*p != 0x55555555) {
	121	printf ("DRAM test fails at: %08x\n", (uint) p);
	122	return 1;
	123	}
	124	}
	125
	126	printf("DRAM test passed.\n");
	127	return 0;
	128	}
	129	#endif
	130
837f1ba0 ES	131	#ifdef CONFIG_PCI1
	132	static struct pci_controller pci1_hose;
	133	#endif
	134
	135	#ifdef CONFIG_PCIE1
	136	static struct pci_controller pcie1_hose;
	137	#endif
	138
	139	#ifdef CONFIG_PCIE2
	140	static struct pci_controller pcie2_hose;
	141	#endif
	142
	143	#ifdef CONFIG_PCIE3
	144	static struct pci_controller pcie3_hose;
	145	#endif
	146
	147	int first_free_busno=0;
	148
	149	void
	150	pci_init_board(void)
	151	{
	152	volatile immap_t immap = (immap_t )CFG_IMMR;
	153	volatile ccsr_gur_t *gur = &immap->im_gur;
	154	uint devdisr = gur->devdisr;
	155	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	156	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	157
	158	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	159	devdisr, io_sel, host_agent);
	160
	161	if (io_sel & 1) {
	162	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	163	printf (" eTSEC1 is in sgmii mode.\n");
	164	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	165	printf (" eTSEC3 is in sgmii mode.\n");
	166	}
	167
	168	#ifdef CONFIG_PCIE3
	169	{
	170	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCIE3_ADDR;
	171	extern void fsl_pci_init(struct pci_controller *hose);
	172	struct pci_controller *hose = &pcie3_hose;
	173	int pcie_ep = (host_agent == 3);
	174	int pcie_configured = io_sel >= 1;
	175
	176	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	177	printf ("\n PCIE3 connected to ULI as %s (base address %x)",
	178	pcie_ep ? "End Point" : "Root Complex",
	179	(uint)pci);
	180	if (pci->pme_msg_det) {
	181	pci->pme_msg_det = 0xffffffff;
	182	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	183	}
	184	printf ("\n");
	185
	186	/* inbound */
	187	pci_set_region(hose->regions + 0,
	188	CFG_PCI_MEMORY_BUS,
	189	CFG_PCI_MEMORY_PHYS,
	190	CFG_PCI_MEMORY_SIZE,
	191	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	192
	193	/* outbound memory */
	194	pci_set_region(hose->regions + 1,
195	CFG_PCIE3_MEM_BASE,
196	CFG_PCIE3_MEM_PHYS,
197	CFG_PCIE3_MEM_SIZE,
198	PCI_REGION_MEM);
199
200	/* outbound io */
201	pci_set_region(hose->regions + 2,
202	CFG_PCIE3_IO_BASE,
203	CFG_PCIE3_IO_PHYS,
204	CFG_PCIE3_IO_SIZE,
205	PCI_REGION_IO);
206
207	hose->region_count = 3;
208	#ifdef CFG_PCIE3_MEM_BASE2
209	/* outbound memory */
210	pci_set_region(hose->regions + 3,
211	CFG_PCIE3_MEM_BASE2,
212	CFG_PCIE3_MEM_PHYS2,
213	CFG_PCIE3_MEM_SIZE2,
214	PCI_REGION_MEM);
215	hose->region_count++;
216	#endif
217	hose->first_busno=first_free_busno;
218	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
219
220	fsl_pci_init(hose);
221
222	first_free_busno=hose->last_busno+1;
223	printf (" PCIE3 on bus %02x - %02x\n",
224	hose->first_busno,hose->last_busno);
225
56a92705 KG	226	/*
	227	* Activate ULI1575 legacy chip by performing a fake
	228	* memory access. Needed to make ULI RTC work.
	229	*/
	230	in_be32(CFG_PCIE3_MEM_BASE);
837f1ba0 ES	231	} else {
	232	printf (" PCIE3: disabled\n");
	233	}
	234
	235	}
	236	#else
	237	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
	238	#endif
	239
	240	#ifdef CONFIG_PCIE1
	241	{
	242	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCIE1_ADDR;
	243	extern void fsl_pci_init(struct pci_controller *hose);
	244	struct pci_controller *hose = &pcie1_hose;
	245	int pcie_ep = (host_agent == 5);
	246	int pcie_configured = io_sel & 6;
	247
	248	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	249	printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
	250	pcie_ep ? "End Point" : "Root Complex",
	251	(uint)pci);
	252	if (pci->pme_msg_det) {
	253	pci->pme_msg_det = 0xffffffff;
	254	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	255	}
	256	printf ("\n");
	257
	258	/* inbound */
	259	pci_set_region(hose->regions + 0,
	260	CFG_PCI_MEMORY_BUS,
	261	CFG_PCI_MEMORY_PHYS,
	262	CFG_PCI_MEMORY_SIZE,
	263	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	264
	265	/* outbound memory */
	266	pci_set_region(hose->regions + 1,
	267	CFG_PCIE1_MEM_BASE,
	268	CFG_PCIE1_MEM_PHYS,
	269	CFG_PCIE1_MEM_SIZE,
	270	PCI_REGION_MEM);
	271
	272	/* outbound io */
	273	pci_set_region(hose->regions + 2,
	274	CFG_PCIE1_IO_BASE,
	275	CFG_PCIE1_IO_PHYS,
	276	CFG_PCIE1_IO_SIZE,
	277	PCI_REGION_IO);
	278
	279	hose->region_count = 3;
	280	#ifdef CFG_PCIE1_MEM_BASE2
	281	/* outbound memory */
	282	pci_set_region(hose->regions + 3,
	283	CFG_PCIE1_MEM_BASE2,
	284	CFG_PCIE1_MEM_PHYS2,
	285	CFG_PCIE1_MEM_SIZE2,
	286	PCI_REGION_MEM);
	287	hose->region_count++;
	288	#endif
	289	hose->first_busno=first_free_busno;
	290
	291	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	292
	293	fsl_pci_init(hose);
	294
295	first_free_busno=hose->last_busno+1;
296	printf(" PCIE1 on bus %02x - %02x\n",
297	hose->first_busno,hose->last_busno);
298
299	} else {
300	printf (" PCIE1: disabled\n");
301	}
302
303	}
304	#else
305	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
306	#endif
307
308	#ifdef CONFIG_PCIE2
309	{
310	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCIE2_ADDR;
311	extern void fsl_pci_init(struct pci_controller *hose);
312	struct pci_controller *hose = &pcie2_hose;
313	int pcie_ep = (host_agent == 3);
314	int pcie_configured = io_sel & 4;
315
316	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
317	printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
318	pcie_ep ? "End Point" : "Root Complex",
319	(uint)pci);
320	if (pci->pme_msg_det) {
321	pci->pme_msg_det = 0xffffffff;
322	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
323	}
324	printf ("\n");
325
326	/* inbound */
327	pci_set_region(hose->regions + 0,
328	CFG_PCI_MEMORY_BUS,
329	CFG_PCI_MEMORY_PHYS,
330	CFG_PCI_MEMORY_SIZE,
331	PCI_REGION_MEM \| PCI_REGION_MEMORY);
332
333	/* outbound memory */
334	pci_set_region(hose->regions + 1,
335	CFG_PCIE2_MEM_BASE,
336	CFG_PCIE2_MEM_PHYS,
337	CFG_PCIE2_MEM_SIZE,
338	PCI_REGION_MEM);
339
340	/* outbound io */
341	pci_set_region(hose->regions + 2,
342	CFG_PCIE2_IO_BASE,
343	CFG_PCIE2_IO_PHYS,
344	CFG_PCIE2_IO_SIZE,
345	PCI_REGION_IO);
346
347	hose->region_count = 3;
348	#ifdef CFG_PCIE2_MEM_BASE2
349	/* outbound memory */
350	pci_set_region(hose->regions + 3,
351	CFG_PCIE2_MEM_BASE2,
352	CFG_PCIE2_MEM_PHYS2,
353	CFG_PCIE2_MEM_SIZE2,
354	PCI_REGION_MEM);
355	hose->region_count++;
356	#endif
357	hose->first_busno=first_free_busno;
358	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
359
360	fsl_pci_init(hose);
361	first_free_busno=hose->last_busno+1;
362	printf (" PCIE2 on bus %02x - %02x\n",
363	hose->first_busno,hose->last_busno);
364
365	} else {
366	printf (" PCIE2: disabled\n");
367	}
368
369	}
370	#else
371	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
372	#endif
373
374
375	#ifdef CONFIG_PCI1
376	{
377	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI1_ADDR;
378	extern void fsl_pci_init(struct pci_controller *hose);
379	struct pci_controller *hose = &pci1_hose;
380
381	uint pci_agent = (host_agent == 6);
382	uint pci_speed = 66666000; /get_clock_freq (); PCI PSPEED in [4:5] /
383	uint pci_32 = 1;
384	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
385	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
386
387
388	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
389	printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
390	(pci_32) ? 32 : 64,
391	(pci_speed == 33333000) ? "33" :
392	(pci_speed == 66666000) ? "66" : "unknown",
393	pci_clk_sel ? "sync" : "async",
394	pci_agent ? "agent" : "host",
395	pci_arb ? "arbiter" : "external-arbiter",
396	(uint)pci
397	);
398
399	/* inbound */
400	pci_set_region(hose->regions + 0,
401	CFG_PCI_MEMORY_BUS,
402	CFG_PCI_MEMORY_PHYS,
403	CFG_PCI_MEMORY_SIZE,
404	PCI_REGION_MEM \| PCI_REGION_MEMORY);
405
406	/* outbound memory */
407	pci_set_region(hose->regions + 1,
408	CFG_PCI1_MEM_BASE,
409	CFG_PCI1_MEM_PHYS,
410	CFG_PCI1_MEM_SIZE,
411	PCI_REGION_MEM);
412
413	/* outbound io */
414	pci_set_region(hose->regions + 2,
415	CFG_PCI1_IO_BASE,
416	CFG_PCI1_IO_PHYS,
417	CFG_PCI1_IO_SIZE,
418	PCI_REGION_IO);
419	hose->region_count = 3;
420	#ifdef CFG_PCIE3_MEM_BASE2
421	/* outbound memory */
422	pci_set_region(hose->regions + 3,
423	CFG_PCIE3_MEM_BASE2,
424	CFG_PCIE3_MEM_PHYS2,
425	CFG_PCIE3_MEM_SIZE2,
426	PCI_REGION_MEM);
427	hose->region_count++;
428	#endif
429	hose->first_busno=first_free_busno;
430	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
431
432	fsl_pci_init(hose);
433	first_free_busno=hose->last_busno+1;
434	printf ("PCI on bus %02x - %02x\n",
435	hose->first_busno,hose->last_busno);
436	} else {
437	printf (" PCI: disabled\n");
438	}
439	}
440	#else
441	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
442	#endif
443	}
444
445
25d83d7f JL	446	int last_stage_init(void)
	447	{
	448	return 0;
	449	}
	450
	451
	452	unsigned long
	453	get_board_sys_clk(ulong dummy)
	454	{
	455	u8 i, go_bit, rd_clks;
	456	ulong val = 0;
	457
	458	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	459	go_bit &= 0x01;
	460
	461	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	462	rd_clks &= 0x1C;
	463
	464	/*
	465	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	466	* should we be using the AUX register. Remember, we also set the
	467	* GO bit to boot from the alternate bank on the on-board flash
	468	*/
	469
	470	if (go_bit) {
	471	if (rd_clks == 0x1c)
	472	i = in8(PIXIS_BASE + PIXIS_AUX);
	473	else
	474	i = in8(PIXIS_BASE + PIXIS_SPD);
	475	} else {
	476	i = in8(PIXIS_BASE + PIXIS_SPD);
	477	}
	478
	479	i &= 0x07;
	480
	481	switch (i) {
	482	case 0:
	483	val = 33333333;
	484	break;
	485	case 1:
	486	val = 40000000;
	487	break;
	488	case 2:
	489	val = 50000000;
	490	break;
	491	case 3:
	492	val = 66666666;
	493	break;
	494	case 4:
	495	val = 83000000;
	496	break;
	497	case 5:
	498	val = 100000000;
	499	break;
	500	case 6:
	501	val = 133333333;
	502	break;
	503	case 7:
	504	val = 166666666;
	505	break;
	506	}
	507
	508	return val;
	509	}
510
511	#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
512	void
513	ft_board_setup(void blob, bd_t bd)
514	{
2f15278c WD	515	u32 *p;
2f15278c WD	516	int len;
25d83d7f	517
2f15278c	518	ft_cpu_setup(blob, bd);
25d83d7f	519
837f1ba0 ES	520	p = ft_get_prop(blob, "/memory/reg", &len);
	521	if (p != NULL) {
	522	*p++ = cpu_to_be32(bd->bi_memstart);
	523	*p = cpu_to_be32(bd->bi_memsize);
	524	}
f75e89e9 ES	525	#ifdef CONFIG_PCI1
	526	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
	527	if (p != NULL) {
	528	p[0] = 0;
	529	p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
	530	debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	531	}
	532	#endif
837f1ba0	533	#ifdef CONFIG_PCIE1
f75e89e9	534	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
837f1ba0 ES	535	if (p != NULL) {
	536	p[0] = 0;
	537	p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
	538	debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	539	}
	540	#endif
	541	#ifdef CONFIG_PCIE2
f75e89e9	542	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
837f1ba0 ES	543	if (p != NULL) {
	544	p[0] = 0;
	545	p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
	546	debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	547	}
	548	#endif
	549	#ifdef CONFIG_PCIE3
f75e89e9	550	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
837f1ba0 ES	551	if (p != NULL) {
	552	p[0] = 0;
	553	p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
	554	debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
	555	}
	556	#endif
25d83d7f JL	557	}
25d83d7f JL	558	#endif