[thirdparty/u-boot.git] / board / freescale / mpc8544ds / mpc8544ds.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <command.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>

#include "../common/sgmii_riser.h"

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	u8 vboot;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	vboot = in_8(pixis_base + PIXIS_VBOOT);
	if (vboot & PIXIS_VBOOT_FMAP)
		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	else
		puts ("Promjet\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct fsl_pci_info pci_info;
	u32 devdisr, pordevsr, io_sel;
	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	int first_free_busno = 0;

	int pcie_ep, pcie_configured;

	devdisr = in_be32(&gur->devdisr);
	pordevsr = in_be32(&gur->pordevsr);
	porpllsr = in_be32(&gur->porpllsr);
	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);

	puts("\n");

#ifdef CONFIG_PCIE3
	pcie_configured = is_serdes_configured(PCIE3);

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
		/* contains both PCIE3 MEM & IO space */
		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
				LAW_TRGT_IF_PCIE_3);
		SET_STD_PCIE_INFO(pci_info, 3);
		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);

		/* outbound memory */
		pci_set_region(&pcie3_hose.regions[0],
			       CONFIG_SYS_PCIE3_MEM_BUS2,
			       CONFIG_SYS_PCIE3_MEM_PHYS2,
			       CONFIG_SYS_PCIE3_MEM_SIZE2,
			       PCI_REGION_MEM);

		pcie3_hose.region_count = 1;

		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
			pcie_ep ? "Endpoint" : "Root Complex",
			pci_info.regs);
		first_free_busno = fsl_pci_init_port(&pci_info,
					&pcie3_hose, first_free_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
	} else {
		printf("PCIE3: disabled\n");
	}
	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif

#ifdef CONFIG_PCIE1
	SET_STD_PCIE_INFO(pci_info, 1);
	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
#else
	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
#endif

#ifdef CONFIG_PCIE2
	SET_STD_PCIE_INFO(pci_info, 2);
	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
#else
	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
#endif

#ifdef CONFIG_PCI1
	pci_speed = 66666000;
	pci_32 = 1;
	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			pci_info.regs);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}

int last_stage_init(void)
{
	return 0;
}


unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	go_bit = in_8(pixis_base + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in_8(pixis_base + PIXIS_AUX);
		else
			i = in_8(pixis_base + PIXIS_SPD);
	} else {
		i = in_8(pixis_base + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333333;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66666666;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 133333333;
		break;
	case 7:
		val = 166666666;
		break;
	}

	return val;
}


#define MIIM_CIS8204_SLED_CON		0x1b
#define MIIM_CIS8204_SLEDCON_INIT	0x1115
/*
 * Hack to write all 4 PHYs with the LED values
 */
int board_phy_config(struct phy_device *phydev)
{
	static int do_once;
	uint phyid;
	struct mii_dev *bus = phydev->bus;

	if (phydev->drv->config)
		phydev->drv->config(phydev);
	if (do_once)
		return 0;

	for (phyid = 0; phyid < 4; phyid++)
		bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
				MIIM_CIS8204_SLEDCON_INIT);

	do_once = 1;

	return 0;
}


int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[2];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	if (is_serdes_configured(SGMII_TSEC1)) {
		puts("eTSEC1 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

	if (is_serdes_configured(SGMII_TSEC1) ||
	    is_serdes_configured(SGMII_TSEC3)) {
		fsl_sgmii_riser_init(tsec_info, num);
	}

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);
#endif
	return pci_eth_init(bis);
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
25d83d7f	2	/*
6525d51f	3	* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
25d83d7f JL	4	*/
	5
	6	#include <common.h>
	7	#include <command.h>
2cf431c2	8	#include <init.h>
90526e9f	9	#include <net.h>
837f1ba0	10	#include <pci.h>
25d83d7f	11	#include <asm/processor.h>
1167a2fd	12	#include <asm/mmu.h>
25d83d7f	13	#include <asm/immap_85xx.h>
c8514622	14	#include <asm/fsl_pci.h>
5614e71b	15	#include <fsl_ddr_sdram.h>
5d27e02c	16	#include <asm/fsl_serdes.h>
56a92705	17	#include <asm/io.h>
25d83d7f	18	#include <miiphy.h>
b08c8c48	19	#include <linux/libfdt.h>
addce57e	20	#include <fdt_support.h>
063c1263	21	#include <fsl_mdio.h>
216f2a71	22	#include <tsec.h>
0b252f50	23	#include <netdev.h>
25d83d7f	24
216f2a71	25	#include "../common/sgmii_riser.h"
25d83d7f	26
25d83d7f JL	27	int checkboard (void)
25d83d7f JL	28	{
6d0f6bcf	29	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	30	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	31	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6bb5b412 KG	32	u8 vboot;
6bb5b412 KG	33	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	34
2f15278c	35	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	36	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
25d83d7f	37	}
6bb5b412 KG	38	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
	39	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	40	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	41	in_8(pixis_base + PIXIS_PVER));
	42
	43	vboot = in_8(pixis_base + PIXIS_VBOOT);
	44	if (vboot & PIXIS_VBOOT_FMAP)
	45	printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
	46	else
	47	puts ("Promjet\n");
25d83d7f	48
837f1ba0 ES	49	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	50	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	51	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	52	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	53
25d83d7f JL	54	return 0;
	55	}
	56
837f1ba0 ES	57	#ifdef CONFIG_PCI1
	58	static struct pci_controller pci1_hose;
	59	#endif
	60
837f1ba0 ES	61	#ifdef CONFIG_PCIE3
	62	static struct pci_controller pcie3_hose;
	63	#endif
	64
645d5a78	65	void pci_init_board(void)
837f1ba0	66	{
6d0f6bcf	67	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
64a1686a	68	struct fsl_pci_info pci_info;
645d5a78 KG	69	u32 devdisr, pordevsr, io_sel;
	70	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
	71	int first_free_busno = 0;
645d5a78 KG	72
645d5a78 KG	73	int pcie_ep, pcie_configured;
837f1ba0	74
645d5a78 KG	75	devdisr = in_be32(&gur->devdisr);
	76	pordevsr = in_be32(&gur->pordevsr);
	77	porpllsr = in_be32(&gur->porpllsr);
	78	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	79
	80	debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
837f1ba0	81
645d5a78	82	puts("\n");
837f1ba0 ES	83
837f1ba0 ES	84	#ifdef CONFIG_PCIE3
5d27e02c	85	pcie_configured = is_serdes_configured(PCIE3);
837f1ba0	86
645d5a78	87	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
64a1686a KG	88	/* contains both PCIE3 MEM & IO space */
	89	set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
	90	LAW_TRGT_IF_PCIE_3);
	91	SET_STD_PCIE_INFO(pci_info, 3);
	92	pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
	93
837f1ba0	94	/* outbound memory */
645d5a78	95	pci_set_region(&pcie3_hose.regions[0],
10795f42	96	CONFIG_SYS_PCIE3_MEM_BUS2,
6d0f6bcf JCPV	97	CONFIG_SYS_PCIE3_MEM_PHYS2,
6d0f6bcf JCPV	98	CONFIG_SYS_PCIE3_MEM_SIZE2,
837f1ba0	99	PCI_REGION_MEM);
837f1ba0	100
645d5a78	101	pcie3_hose.region_count = 1;
64a1686a	102
8ca78f2c PT	103	printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
8ca78f2c PT	104	pcie_ep ? "Endpoint" : "Root Complex",
64a1686a KG	105	pci_info.regs);
64a1686a KG	106	first_free_busno = fsl_pci_init_port(&pci_info,
645d5a78	107	&pcie3_hose, first_free_busno);
837f1ba0	108
56a92705 KG	109	/*
	110	* Activate ULI1575 legacy chip by performing a fake
	111	* memory access. Needed to make ULI RTC work.
	112	*/
10795f42	113	in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
837f1ba0	114	} else {
8ca78f2c	115	printf("PCIE3: disabled\n");
837f1ba0	116	}
645d5a78	117	puts("\n");
837f1ba0	118	#else
645d5a78	119	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
837f1ba0 ES	120	#endif
	121
	122	#ifdef CONFIG_PCIE1
64a1686a KG	123	SET_STD_PCIE_INFO(pci_info, 1);
64a1686a KG	124	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
837f1ba0	125	#else
64a1686a	126	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
837f1ba0 ES	127	#endif
	128
	129	#ifdef CONFIG_PCIE2
64a1686a KG	130	SET_STD_PCIE_INFO(pci_info, 2);
64a1686a KG	131	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
837f1ba0	132	#else
64a1686a	133	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
837f1ba0 ES	134	#endif
837f1ba0 ES	135
837f1ba0	136	#ifdef CONFIG_PCI1
645d5a78 KG	137	pci_speed = 66666000;
	138	pci_32 = 1;
	139	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	140	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
837f1ba0 ES	141
837f1ba0 ES	142	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
64a1686a KG	143	SET_STD_PCI_INFO(pci_info, 1);
	144	set_next_law(pci_info.mem_phys,
	145	law_size_bits(pci_info.mem_size), pci_info.law);
	146	set_next_law(pci_info.io_phys,
	147	law_size_bits(pci_info.io_size), pci_info.law);
	148
	149	pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c	150	printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
837f1ba0 ES	151	(pci_32) ? 32 : 64,
	152	(pci_speed == 33333000) ? "33" :
	153	(pci_speed == 66666000) ? "66" : "unknown",
	154	pci_clk_sel ? "sync" : "async",
	155	pci_agent ? "agent" : "host",
	156	pci_arb ? "arbiter" : "external-arbiter",
64a1686a	157	pci_info.regs);
837f1ba0	158
64a1686a	159	first_free_busno = fsl_pci_init_port(&pci_info,
645d5a78	160	&pci1_hose, first_free_busno);
837f1ba0	161	} else {
8ca78f2c	162	printf("PCI: disabled\n");
837f1ba0	163	}
645d5a78 KG	164
645d5a78 KG	165	puts("\n");
837f1ba0	166	#else
645d5a78	167	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
837f1ba0 ES	168	#endif
	169	}
	170
25d83d7f JL	171	int last_stage_init(void)
	172	{
	173	return 0;
	174	}
	175
	176
	177	unsigned long
	178	get_board_sys_clk(ulong dummy)
	179	{
	180	u8 i, go_bit, rd_clks;
	181	ulong val = 0;
048e7efe	182	u8 pixis_base = (u8 )PIXIS_BASE;
25d83d7f	183
048e7efe	184	go_bit = in_8(pixis_base + PIXIS_VCTL);
25d83d7f JL	185	go_bit &= 0x01;
25d83d7f JL	186
048e7efe	187	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
25d83d7f JL	188	rd_clks &= 0x1C;
	189
	190	/*
	191	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	192	* should we be using the AUX register. Remember, we also set the
	193	* GO bit to boot from the alternate bank on the on-board flash
	194	*/
	195
	196	if (go_bit) {
	197	if (rd_clks == 0x1c)
048e7efe	198	i = in_8(pixis_base + PIXIS_AUX);
25d83d7f	199	else
048e7efe	200	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f	201	} else {
048e7efe	202	i = in_8(pixis_base + PIXIS_SPD);
25d83d7f JL	203	}
	204
	205	i &= 0x07;
	206
	207	switch (i) {
	208	case 0:
	209	val = 33333333;
	210	break;
	211	case 1:
	212	val = 40000000;
	213	break;
	214	case 2:
	215	val = 50000000;
	216	break;
	217	case 3:
	218	val = 66666666;
	219	break;
	220	case 4:
	221	val = 83000000;
	222	break;
	223	case 5:
	224	val = 100000000;
	225	break;
	226	case 6:
	227	val = 133333333;
	228	break;
	229	case 7:
	230	val = 166666666;
	231	break;
	232	}
	233
	234	return val;
	235	}
	236
063c1263 AF	237
	238	#define MIIM_CIS8204_SLED_CON 0x1b
	239	#define MIIM_CIS8204_SLEDCON_INIT 0x1115
	240	/*
	241	* Hack to write all 4 PHYs with the LED values
	242	*/
	243	int board_phy_config(struct phy_device *phydev)
	244	{
	245	static int do_once;
	246	uint phyid;
	247	struct mii_dev *bus = phydev->bus;
	248
9fafe7da TK	249	if (phydev->drv->config)
9fafe7da TK	250	phydev->drv->config(phydev);
063c1263 AF	251	if (do_once)
	252	return 0;
	253
	254	for (phyid = 0; phyid < 4; phyid++)
	255	bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
	256	MIIM_CIS8204_SLEDCON_INIT);
	257
	258	do_once = 1;
	259
	260	return 0;
	261	}
	262
	263
216f2a71 AF	264	int board_eth_init(bd_t *bis)
216f2a71 AF	265	{
0b252f50	266	#ifdef CONFIG_TSEC_ENET
063c1263	267	struct fsl_pq_mdio_info mdio_info;
216f2a71	268	struct tsec_info_struct tsec_info[2];
216f2a71 AF	269	int num = 0;
	270
	271	#ifdef CONFIG_TSEC1
	272	SET_STD_TSEC_INFO(tsec_info[num], 1);
058d7dc7 KG	273	if (is_serdes_configured(SGMII_TSEC1)) {
058d7dc7 KG	274	puts("eTSEC1 is in sgmii mode.\n");
216f2a71	275	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	276	}
216f2a71 AF	277	num++;
	278	#endif
	279	#ifdef CONFIG_TSEC3
	280	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	281	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	282	puts("eTSEC3 is in sgmii mode.\n");
216f2a71	283	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	284	}
216f2a71 AF	285	num++;
	286	#endif
	287
	288	if (!num) {
	289	printf("No TSECs initialized\n");
	290
	291	return 0;
	292	}
	293
058d7dc7 KG	294	if (is_serdes_configured(SGMII_TSEC1) \|\|
058d7dc7 KG	295	is_serdes_configured(SGMII_TSEC3)) {
216f2a71	296	fsl_sgmii_riser_init(tsec_info, num);
058d7dc7	297	}
216f2a71	298
063c1263 AF	299	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	300	mdio_info.name = DEFAULT_MII_NAME;
	301	fsl_pq_mdio_init(bis, &mdio_info);
216f2a71 AF	302
216f2a71 AF	303	tsec_eth_init(bis, tsec_info, num);
216f2a71	304	#endif
0b252f50 BW	305	return pci_eth_init(bis);
0b252f50 BW	306	}
216f2a71	307
addce57e	308	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	309	int ft_board_setup(void blob, bd_t bd)
25d83d7f	310	{
2f15278c	311	ft_cpu_setup(blob, bd);
25d83d7f	312
6525d51f	313	FT_FSL_PCI_SETUP;
2dba0dea	314
feede8b0 AF	315	#ifdef CONFIG_FSL_SGMII_RISER
	316	fsl_sgmii_riser_fdt_fixup(blob);
	317	#endif
e895a4b0 SG	318
e895a4b0 SG	319	return 0;
25d83d7f JL	320	}
25d83d7f JL	321	#endif