[people/ms/u-boot.git] / board / freescale / mpc8560ads / init.S

/*
 * Copyright 2004 Freescale Semiconductor.
 * Copyright (C) 2002,2003, Motorola Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>


/*
 * TLB0 and TLB1 Entries
 *
 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
 * these TLB entries are established.
 *
 * The TLB entries for DDR are dynamically setup in spd_sdram()
 * and use TLB1 Entries 8 through 15 as needed according to the
 * size of DDR memory.
 *
 * MAS0: tlbsel, esel, nv
 * MAS1: valid, iprot, tid, ts, tsize
 * MAS2: epn, sharen, x0, x1, w, i, m, g, e
 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
 */

#define	entry_start \
	mflr	r1 	;	\
	bl	0f 	;

#define	entry_end \
0:	mflr	r0	;	\
	mtlr	r1	;	\
	blr		;


	.section	.bootpg, "ax"
	.globl	tlb1_entry
tlb1_entry:
	entry_start

	/*
	 * Number of TLB0 and TLB1 entries in the following table
	 */
	.long 13

#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
	/*
	 * TLB0		4K	Non-cacheable, guarded
	 * 0xff700000	4K	Initial CCSRBAR mapping
	 *
	 * This ends up at a TLB0 Index==0 entry, and must not collide
	 * with other TLB0 Entries.
	 */
	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
#else
#error("Update the number of table entries in tlb1_entry")
#endif

	/*
	 * TLB0		16K	Cacheable, non-guarded
	 * 0xd001_0000	16K	Temporary Global data for initialization
	 *
	 * Use four 4K TLB0 entries.  These entries must be cacheable
	 * as they provide the bootstrap memory before the memory
	 * controler and real memory have been configured.
	 *
	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
	 * and must not collide with other TLB0 entries.
	 */
	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
			0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
			0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
			0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
			0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
			0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
			0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(0, 0, 0)
	.long TLB1_MAS1(1, 0, 0, 0, 0)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
			0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
			0,0,0,0,0,1,0,1,0,1)


	/*
	 * TLB 0:	16M	Non-cacheable, guarded
	 * 0xff000000	16M	FLASH
	 * Out of reset this entry is only 4K.
	 */
	.long TLB1_MAS0(1, 0, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 1:	256M	Non-cacheable, guarded
	 * 0x80000000	256M	PCI1 MEM First half
	 */
	.long TLB1_MAS0(1, 1, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 2:	256M	Non-cacheable, guarded
	 * 0x90000000	256M	PCI1 MEM Second half
	 */
	.long TLB1_MAS0(1, 2, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
			0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
			0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 3:	256M	Non-cacheable, guarded
	 * 0xc0000000	256M	Rapid IO MEM First half
	 */
	.long TLB1_MAS0(1, 3, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 4:	256M	Non-cacheable, guarded
	 * 0xd0000000	256M	Rapid IO MEM Second half
	 */
	.long TLB1_MAS0(1, 4, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
			0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
			0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 5:	64M	Non-cacheable, guarded
	 * 0xe000_0000	1M	CCSRBAR
	 * 0xe200_0000	16M	PCI1 IO
	 */
	.long TLB1_MAS0(1, 5, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 6:	64M	Cacheable, non-guarded
	 * 0xf000_0000	64M	LBC SDRAM
	 */
	.long TLB1_MAS0(1, 6, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)

	/*
	 * TLB 7:	16K	Non-cacheable, guarded
	 * 0xf8000000	16K	BCSR registers
	 */
	.long TLB1_MAS0(1, 7, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)

#if !defined(CONFIG_SPD_EEPROM)
	/*
	 * TLB 8, 9:	128M	DDR
	 * 0x00000000	64M	DDR System memory
	 * 0x04000000	64M	DDR System memory
	 * Without SPD EEPROM configured DDR, this must be setup manually.
	 * Make sure the TLB count at the top of this table is correct.
	 * Likely it needs to be increased by two for these entries.
	 */
#error("Update the number of table entries in tlb1_entry")
	.long TLB1_MAS0(1, 8, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)

	.long TLB1_MAS0(1, 9, 0)
	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
			0,0,0,0,0,0,0,0)
	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
			0,0,0,0,0,1,0,1,0,1)
#endif

	entry_end

/*
 * LAW(Local Access Window) configuration:
 *
 * 0x0000_0000     0x7fff_ffff     DDR                     2G
 * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
 * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
 * 0xe000_0000     0xe000_ffff     CCSR                    1M
 * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
 * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
 * 0xf800_0000     0xf80f_ffff     BCSR                    1M
 * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
 *
 * Notes:
 *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 *    If flash is 8M at default position (last 8M), no LAW needed.
 */

#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
#else
#define LAWBAR0 0
#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif

#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))

/*
 * This is not so much the SDRAM map as it is the whole localbus map.
 */
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))

#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))

/*
 * Rapid IO at 0xc000_0000 for 512 M
 */
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))


	.section .bootpg, "ax"
	.globl	law_entry
law_entry:
	entry_start
	.long 0x05
	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
	.long LAWBAR4,LAWAR4
	entry_end
Commit	Line	Data
42d1f039	1	/*
97d80fc3	2	* Copyright 2004 Freescale Semiconductor.
9aea9530 WD	3	* Copyright (C) 2002,2003, Motorola Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
42d1f039 WD	24
	25	#include <ppc_asm.tmpl>
	26	#include <ppc_defs.h>
	27	#include <asm/cache.h>
	28	#include <asm/mmu.h>
	29	#include <config.h>
	30	#include <mpc85xx.h>
	31
9aea9530 WD	32
	33	/*
	34	* TLB0 and TLB1 Entries
	35	*
	36	* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
	37	* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
	38	* these TLB entries are established.
	39	*
	40	* The TLB entries for DDR are dynamically setup in spd_sdram()
	41	* and use TLB1 Entries 8 through 15 as needed according to the
	42	* size of DDR memory.
	43	*
	44	* MAS0: tlbsel, esel, nv
	45	* MAS1: valid, iprot, tid, ts, tsize
	46	* MAS2: epn, sharen, x0, x1, w, i, m, g, e
	47	* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
	48	*/
	49
42d1f039 WD	50	#define entry_start \
	51	mflr r1 ; \
	52	bl 0f ;
	53
	54	#define entry_end \
	55	0: mflr r0 ; \
	56	mtlr r1 ; \
	57	blr ;
	58
42d1f039 WD	59
	60	.section .bootpg, "ax"
	61	.globl tlb1_entry
	62	tlb1_entry:
	63	entry_start
	64
9aea9530 WD	65	/*
	66	* Number of TLB0 and TLB1 entries in the following table
	67	*/
	68	.long 13
	69
	70	#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
	71	/*
	72	* TLB0 4K Non-cacheable, guarded
	73	* 0xff700000 4K Initial CCSRBAR mapping
	74	*
	75	* This ends up at a TLB0 Index==0 entry, and must not collide
	76	* with other TLB0 Entries.
	77	*/
	78	.long TLB1_MAS0(0, 0, 0)
	79	.long TLB1_MAS1(1, 0, 0, 0, 0)
	80	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
	81	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
	82	#else
	83	#error("Update the number of table entries in tlb1_entry")
	84	#endif
42d1f039	85
0ac6f8b7	86	/*
9aea9530 WD	87	* TLB0 16K Cacheable, non-guarded
	88	* 0xd001_0000 16K Temporary Global data for initialization
	89	*
	90	* Use four 4K TLB0 entries. These entries must be cacheable
	91	* as they provide the bootstrap memory before the memory
	92	* controler and real memory have been configured.
	93	*
	94	* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
	95	* and must not collide with other TLB0 entries.
0ac6f8b7	96	*/
9aea9530 WD	97	.long TLB1_MAS0(0, 0, 0)
	98	.long TLB1_MAS1(1, 0, 0, 0, 0)
	99	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
	100	0,0,0,0,0,0,0,0)
	101	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
	102	0,0,0,0,0,1,0,1,0,1)
0ac6f8b7	103
9aea9530 WD	104	.long TLB1_MAS0(0, 0, 0)
	105	.long TLB1_MAS1(1, 0, 0, 0, 0)
	106	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
	107	0,0,0,0,0,0,0,0)
	108	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
	109	0,0,0,0,0,1,0,1,0,1)
0ac6f8b7	110
9aea9530 WD	111	.long TLB1_MAS0(0, 0, 0)
	112	.long TLB1_MAS1(1, 0, 0, 0, 0)
	113	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
	114	0,0,0,0,0,0,0,0)
	115	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
	116	0,0,0,0,0,1,0,1,0,1)
0ac6f8b7	117
9aea9530 WD	118	.long TLB1_MAS0(0, 0, 0)
	119	.long TLB1_MAS1(1, 0, 0, 0, 0)
	120	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
	121	0,0,0,0,0,0,0,0)
	122	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
	123	0,0,0,0,0,1,0,1,0,1)
	124
	125
	126	/*
	127	* TLB 0: 16M Non-cacheable, guarded
	128	* 0xff000000 16M FLASH
	129	* Out of reset this entry is only 4K.
	130	*/
	131	.long TLB1_MAS0(1, 0, 0)
	132	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
	133	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
	134	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
	135
	136	/*
	137	* TLB 1: 256M Non-cacheable, guarded
	138	* 0x80000000 256M PCI1 MEM First half
	139	*/
	140	.long TLB1_MAS0(1, 1, 0)
	141	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	142	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
	143	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
	144
	145	/*
	146	* TLB 2: 256M Non-cacheable, guarded
	147	* 0x90000000 256M PCI1 MEM Second half
	148	*/
	149	.long TLB1_MAS0(1, 2, 0)
	150	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	151	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
	152	0,0,0,0,1,0,1,0)
	153	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
	154	0,0,0,0,0,1,0,1,0,1)
	155
	156	/*
	157	* TLB 3: 256M Non-cacheable, guarded
	158	* 0xc0000000 256M Rapid IO MEM First half
	159	*/
	160	.long TLB1_MAS0(1, 3, 0)
	161	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	162	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
	163	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
	164
	165	/*
	166	* TLB 4: 256M Non-cacheable, guarded
	167	* 0xd0000000 256M Rapid IO MEM Second half
	168	*/
	169	.long TLB1_MAS0(1, 4, 0)
	170	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
	171	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
	172	0,0,0,0,1,0,1,0)
	173	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
	174	0,0,0,0,0,1,0,1,0,1)
	175
	176	/*
	177	* TLB 5: 64M Non-cacheable, guarded
	178	* 0xe000_0000 1M CCSRBAR
	179	* 0xe200_0000 16M PCI1 IO
	180	*/
	181	.long TLB1_MAS0(1, 5, 0)
182	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
183	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
184	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
185
186	/*
187	* TLB 6: 64M Cacheable, non-guarded
188	* 0xf000_0000 64M LBC SDRAM
189	*/
190	.long TLB1_MAS0(1, 6, 0)
191	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
192	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
193	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
194
195	/*
196	* TLB 7: 16K Non-cacheable, guarded
197	* 0xf8000000 16K BCSR registers
198	*/
199	.long TLB1_MAS0(1, 7, 0)
200	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
201	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
202	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
203
204	#if !defined(CONFIG_SPD_EEPROM)
205	/*
206	* TLB 8, 9: 128M DDR
207	* 0x00000000 64M DDR System memory
208	* 0x04000000 64M DDR System memory
209	* Without SPD EEPROM configured DDR, this must be setup manually.
210	* Make sure the TLB count at the top of this table is correct.
211	* Likely it needs to be increased by two for these entries.
212	*/
213	#error("Update the number of table entries in tlb1_entry")
214	.long TLB1_MAS0(1, 8, 0)
215	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
216	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
217	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
218
219	.long TLB1_MAS0(1, 9, 0)
220	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
221	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
222	0,0,0,0,0,0,0,0)
223	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
224	0,0,0,0,0,1,0,1,0,1)
0ac6f8b7	225	#endif
9aea9530	226
42d1f039 WD	227	entry_end
42d1f039 WD	228
97d80fc3 WD	229	/*
	230	* LAW(Local Access Window) configuration:
	231	*
	232	* 0x0000_0000 0x7fff_ffff DDR 2G
0ac6f8b7 WD	233	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
0ac6f8b7 WD	234	* 0xc000_0000 0xdfff_ffff RapidIO 512M
97d80fc3	235	* 0xe000_0000 0xe000_ffff CCSR 1M
0ac6f8b7	236	* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
97d80fc3 WD	237	* 0xf000_0000 0xf7ff_ffff SDRAM 128M
	238	* 0xf800_0000 0xf80f_ffff BCSR 1M
	239	* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
	240	*
0ac6f8b7 WD	241	* Notes:
	242	* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
	243	* If flash is 8M at default position (last 8M), no LAW needed.
42d1f039 WD	244	*/
	245
	246	#if !defined(CONFIG_SPD_EEPROM)
	247	#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
97d80fc3	248	#define LAWAR0 (LAWAR_EN \| LAWAR_TRGT_IF_DDR \| (LAWAR_SIZE & LAWAR_SIZE_128M))
42d1f039 WD	249	#else
	250	#define LAWBAR0 0
	251	#define LAWAR0 ((LAWAR_TRGT_IF_DDR \| (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
	252	#endif
	253
0ac6f8b7	254	#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
97d80fc3	255	#define LAWAR1 (LAWAR_EN \| LAWAR_TRGT_IF_PCIX \| (LAWAR_SIZE & LAWAR_SIZE_512M))
42d1f039	256
97d80fc3 WD	257	/*
	258	* This is not so much the SDRAM map as it is the whole localbus map.
	259	*/
42d1f039	260	#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
97d80fc3	261	#define LAWAR2 (LAWAR_EN \| LAWAR_TRGT_IF_LBC \| (LAWAR_SIZE & LAWAR_SIZE_256M))
42d1f039	262
362dd830 SS	263	#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
362dd830 SS	264	#define LAWAR3 (LAWAR_EN \| LAWAR_TRGT_IF_PCIX \| (LAWAR_SIZE & LAWAR_SIZE_1M))
97d80fc3 WD	265
	266	/*
	267	* Rapid IO at 0xc000_0000 for 512 M
	268	*/
0ac6f8b7 WD	269	#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
0ac6f8b7 WD	270	#define LAWAR4 (LAWAR_EN \| LAWAR_TRGT_IF_RIO \| (LAWAR_SIZE & LAWAR_SIZE_512M))
97d80fc3 WD	271
97d80fc3 WD	272
42d1f039	273	.section .bootpg, "ax"
97d80fc3	274	.globl law_entry
42d1f039 WD	275	law_entry:
42d1f039 WD	276	entry_start
97d80fc3 WD	277	.long 0x05
	278	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
	279	.long LAWBAR4,LAWAR4
42d1f039	280	entry_end