[thirdparty/u-boot.git] / board / freescale / mpc8560ads / mpc8560ads.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2003,Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_lbc.h>

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif


void local_bus_init(void);


/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*            conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*            conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};


/*
 * MPC8560ADS Board Status & Control Registers
 */
typedef struct bcsr_ {
	volatile unsigned char bcsr0;
	volatile unsigned char bcsr1;
	volatile unsigned char bcsr2;
	volatile unsigned char bcsr3;
	volatile unsigned char bcsr4;
	volatile unsigned char bcsr5;
} bcsr_t;

void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
#endif
	/* reset Giga bit Ethernet port if needed here */

	/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
	bcsr->bcsr2 &= ~FETH2_RST;
	udelay(2);
	bcsr->bcsr2 |=  FETH2_RST;
	udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
	bcsr->bcsr3 &= ~FETH3_RST;
	udelay(2);
	bcsr->bcsr3 |=  FETH3_RST;
	udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
	/* reset PHY */
	miiphy_reset("FCC1", 0x0);

	/* change PHY address to 0x02 */
	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);

	bb_miiphy_write(NULL, 0x02, MII_BMCR,
			BMCR_ANENABLE | BMCR_ANRESTART);
#endif /* CONFIG_MII */
}


int checkboard (void)
{
	puts("Board: ADS\n");

#ifdef CONFIG_PCI
	printf("PCI1: 32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf("PCI1: disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	return 0;
}

/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
	 * If localbus freq is > 133MHz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & LCRR_CLKDIV;
	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}


/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;

	puts("LBC SDRAM: ");
	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
		   "\n       ");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");

	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("sync");

	/*
	 * Configure the SDRAM controller.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
	asm("sync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
phys_size_t fixed_sdram(void)
{
  #ifndef CONFIG_SYS_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
  #endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
      PCI_IDSEL_NUMBER, PCI_ANY_ID,
      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				   PCI_ENET0_MEMADDR,
				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
      } },
    { }
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc85xxads_config_table,
#endif
};

#endif	/* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}


#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = hose.last_busno - hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
42d1f039	1	/*
97d80fc3	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2003,Motorola Inc.
	4	* Xianghua Xiao, (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	9	*/
	10
	11
42d1f039	12	#include <common.h>
9aea9530	13	#include <pci.h>
42d1f039	14	#include <asm/processor.h>
8b625114	15	#include <asm/mmu.h>
42d1f039	16	#include <asm/immap_85xx.h>
8b625114	17	#include <asm/fsl_ddr_sdram.h>
42d1f039	18	#include <ioports.h>
a30a549a	19	#include <spd_sdram.h>
42d1f039	20	#include <miiphy.h>
5ce71580 KG	21	#include <libfdt.h>
5ce71580 KG	22	#include <fdt_support.h>
b0fe93ed	23	#include <asm/fsl_lbc.h>
f5012827	24
d9b94f28	25	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
0ac6f8b7 WD	26	extern void ddr_enable_ecc(unsigned int dram_size);
	27	#endif
	28
0ac6f8b7	29
9aea9530	30	void local_bus_init(void);
0ac6f8b7	31
42d1f039 WD	32
	33	/*
	34	* I/O Port configuration table
	35	*
	36	* if conf is 1, then that port pin will be configured at boot time
	37	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	38	*/
	39
	40	const iop_conf_t iop_conf_tab[4][32] = {
	41
	42	/* Port A configuration */
	43	{ /* conf ppar psor pdir podr pdat */
	44	/* PA31 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxENB */
	45	/* PA30 / { 0, 1, 0, 0, 0, 0 }, / FCC1 TxClav */
	46	/* PA29 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxSOC */
	47	/* PA28 / { 0, 1, 0, 1, 0, 0 }, / FCC1 RxENB */
	48	/* PA27 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxSOC */
	49	/* PA26 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxClav */
	50	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	51	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	52	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
	53	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
	54	/* PA21 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[4] */
	55	/* PA20 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[5] */
	56	/* PA19 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[6] */
	57	/* PA18 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[7] */
	58	/* PA17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[7] */
	59	/* PA16 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[6] */
	60	/* PA15 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[5] */
	61	/* PA14 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[4] */
	62	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
	63	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
	64	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
	65	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
	66	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
	67	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
	68	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	69	/* PA6 / { 0, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
	70	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	71	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	72	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	73	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	74	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FREERUN */
	75	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	76	},
	77
	78	/* Port B configuration */
	79	{ /* conf ppar psor pdir podr pdat */
	80	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	81	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	82	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	83	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	84	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	85	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	86	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	87	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	88	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	89	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	90	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	91	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	92	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	93	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
	94	/* PB17 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
	95	/* PB16 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
96	/* PB15 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
97	/* PB14 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
98	/* PB13 / { 0, 1, 0, 0, 0, 0 }, / FCC3:COL */
99	/* PB12 / { 0, 1, 0, 0, 0, 0 }, / FCC3:CRS */
100	/* PB11 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
101	/* PB10 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
102	/* PB9 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
103	/* PB8 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
104	/* PB7 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
105	/* PB6 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
106	/* PB5 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
107	/* PB4 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
108	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
109	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
110	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
111	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
112	},
113
114	/* Port C */
115	{ /* conf ppar psor pdir podr pdat */
116	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
117	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
118	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
119	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
120	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
121	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
122	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
123	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
124	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
125	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
126	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
127	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
128	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
129	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
130	/* PC17 / { 0, 0, 0, 1, 0, 0 }, / PC17 */
131	/* PC16 / { 0, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
132	/* PC15 / { 1, 1, 0, 0, 0, 0 }, / PC15 */
133	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
134	/* PC13 / { 0, 0, 0, 1, 0, 0 }, / PC13 */
135	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
136	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
137	/* PC10 / { 1, 0, 0, 1, 0, 0 }, / FETHMDC */
138	/* PC9 / { 1, 0, 0, 0, 0, 0 }, / FETHMDIO */
139	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
140	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
141	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
142	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
143	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
144	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
145	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
146	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
147	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
148	},
149
150	/* Port D */
151	{ /* conf ppar psor pdir podr pdat */
152	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
153	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
154	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
155	/* PD28 / { 0, 1, 0, 0, 0, 0 }, / PD28 */
156	/* PD27 / { 0, 1, 1, 1, 0, 0 }, / PD27 */
157	/* PD26 / { 0, 0, 0, 1, 0, 0 }, / PD26 */
158	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
159	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
160	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
161	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
162	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
163	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
164	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
165	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
166	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
167	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
168	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
169	/* PD14 / { 0, 0, 0, 1, 0, 0 }, / LED */
170	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
171	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
172	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
173	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
174	/* PD9 / { 0, 1, 0, 1, 0, 0 }, / SMC1 TXD */
175	/* PD8 / { 0, 1, 0, 0, 0, 0 }, / SMC1 RXD */
176	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
177	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
178	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
179	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
180	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
181	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
182	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
183	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
184	}
185	};
186
0ac6f8b7 WD	187
	188	/*
	189	* MPC8560ADS Board Status & Control Registers
	190	*/
	191	typedef struct bcsr_ {
42d1f039 WD	192	volatile unsigned char bcsr0;
	193	volatile unsigned char bcsr1;
	194	volatile unsigned char bcsr2;
	195	volatile unsigned char bcsr3;
	196	volatile unsigned char bcsr4;
	197	volatile unsigned char bcsr5;
	198	} bcsr_t;
	199
42d1f039 WD	200	void reset_phy (void)
	201	{
	202	#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
6d0f6bcf	203	volatile bcsr_t bcsr = (bcsr_t ) CONFIG_SYS_BCSR;
42d1f039 WD	204	#endif
	205	/* reset Giga bit Ethernet port if needed here */
	206
	207	/* reset the CPM FEC port */
	208	#if (CONFIG_ETHER_INDEX == 2)
	209	bcsr->bcsr2 &= ~FETH2_RST;
	210	udelay(2);
	211	bcsr->bcsr2 \|= FETH2_RST;
	212	udelay(1000);
	213	#elif (CONFIG_ETHER_INDEX == 3)
	214	bcsr->bcsr3 &= ~FETH3_RST;
	215	udelay(2);
	216	bcsr->bcsr3 \|= FETH3_RST;
	217	udelay(1000);
	218	#endif
	219	#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
63ff004c	220	/* reset PHY */
48690d80	221	miiphy_reset("FCC1", 0x0);
63ff004c MB	222
63ff004c MB	223	/* change PHY address to 0x02 */
8ef583a0	224	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
63ff004c	225
8ef583a0 MF	226	bb_miiphy_write(NULL, 0x02, MII_BMCR,
8ef583a0 MF	227	BMCR_ANENABLE \| BMCR_ANRESTART);
42d1f039 WD	228	#endif /* CONFIG_MII */
	229	}
	230
9aea9530	231
42d1f039 WD	232	int checkboard (void)
42d1f039 WD	233	{
97d80fc3	234	puts("Board: ADS\n");
0ac6f8b7 WD	235
0ac6f8b7 WD	236	#ifdef CONFIG_PCI
8ca78f2c	237	printf("PCI1: 32 bit, %d MHz (compiled)\n",
0ac6f8b7 WD	238	CONFIG_SYS_CLK_FREQ / 1000000);
0ac6f8b7 WD	239	#else
8ca78f2c	240	printf("PCI1: disabled\n");
0ac6f8b7	241	#endif
9aea9530 WD	242
	243	/*
	244	* Initialize local bus.
	245	*/
	246	local_bus_init();
	247
97d80fc3	248	return 0;
42d1f039 WD	249	}
42d1f039 WD	250
0ac6f8b7	251	/*
9aea9530	252	* Initialize Local Bus
0ac6f8b7 WD	253	*/
0ac6f8b7 WD	254
9aea9530 WD	255	void
9aea9530 WD	256	local_bus_init(void)
0ac6f8b7	257	{
6d0f6bcf	258	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	259	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
0ac6f8b7	260
9aea9530 WD	261	uint clkdiv;
	262	uint lbc_hz;
	263	sys_info_t sysinfo;
0ac6f8b7 WD	264
0ac6f8b7 WD	265	/*
9aea9530 WD	266	* Errata LBC11.
9aea9530 WD	267	* Fix Local Bus clock glitch when DLL is enabled.
0ac6f8b7	268	*
8ed44d91 WD	269	* If localbus freq is < 66MHz, DLL bypass mode must be used.
8ed44d91 WD	270	* If localbus freq is > 133MHz, DLL can be safely enabled.
9aea9530	271	* Between 66 and 133, the DLL is enabled with an override workaround.
0ac6f8b7	272	*/
9aea9530 WD	273
9aea9530 WD	274	get_sys_info(&sysinfo);
a5d212a2	275	clkdiv = lbc->lcrr & LCRR_CLKDIV;
997399fa	276	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
9aea9530 WD	277
9aea9530 WD	278	if (lbc_hz < 66) {
a2af6a7a	279	lbc->lcrr = CONFIG_SYS_LBC_LCRR \| LCRR_DBYP; /* DLL Bypass */
9aea9530 WD	280
9aea9530 WD	281	} else if (lbc_hz >= 133) {
a2af6a7a	282	lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
0ac6f8b7	283
42d1f039	284	} else {
0ac6f8b7 WD	285	/*
	286	* On REV1 boards, need to change CLKDIV before enable DLL.
	287	* Default CLKDIV is 8, change it to 4 temporarily.
	288	*/
9aea9530	289	uint pvr = get_pvr();
0ac6f8b7	290	uint temp_lbcdll = 0;
97d80fc3 WD	291
97d80fc3 WD	292	if (pvr == PVR_85xx_REV1) {
9aea9530	293	/* FIXME: Justify the high bit here. */
0ac6f8b7	294	lbc->lcrr = 0x10000004;
97d80fc3	295	}
0ac6f8b7	296
a2af6a7a	297	lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
9aea9530 WD	298	udelay(200);
	299
	300	/*
	301	* Sample LBC DLL ctrl reg, upshift it to set the
	302	* override bits.
	303	*/
42d1f039	304	temp_lbcdll = gur->lbcdllcr;
9aea9530 WD	305	gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) \| 0x80000000);
9aea9530 WD	306	asm("sync;isync;msync");
42d1f039	307	}
9aea9530 WD	308	}
	309
	310
	311	/*
	312	* Initialize SDRAM memory on the Local Bus.
	313	*/
70961ba4	314	void lbc_sdram_init(void)
9aea9530	315	{
f51cdaf1	316	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	317	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
9aea9530	318
7ea3871e BB	319	puts("LBC SDRAM: ");
	320	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
	321	"\n ");
0ac6f8b7 WD	322
	323	/*
	324	* Setup SDRAM Base and Option Registers
	325	*/
f51cdaf1 BB	326	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
f51cdaf1 BB	327	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
6d0f6bcf	328	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
9aea9530	329	asm("msync");
0ac6f8b7	330
6d0f6bcf JCPV	331	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	332	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
9aea9530	333	asm("sync");
0ac6f8b7 WD	334
	335	/*
	336	* Configure the SDRAM controller.
	337	*/
6d0f6bcf	338	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
9aea9530	339	asm("sync");
0ac6f8b7	340	*sdram_addr = 0xff;
9aea9530 WD	341	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	342	udelay(100);
0ac6f8b7	343
6d0f6bcf	344	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
9aea9530	345	asm("sync");
0ac6f8b7	346	*sdram_addr = 0xff;
9aea9530 WD	347	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	348	udelay(100);
0ac6f8b7	349
6d0f6bcf	350	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
9aea9530	351	asm("sync");
0ac6f8b7	352	*sdram_addr = 0xff;
9aea9530 WD	353	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	354	udelay(100);
42d1f039	355
6d0f6bcf	356	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
9aea9530	357	asm("sync");
0ac6f8b7	358	*sdram_addr = 0xff;
9aea9530 WD	359	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	360	udelay(100);
42d1f039	361
6d0f6bcf	362	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
9aea9530	363	asm("sync");
0ac6f8b7	364	*sdram_addr = 0xff;
9aea9530 WD	365	ppcDcbf((unsigned long) sdram_addr);
9aea9530 WD	366	udelay(100);
42d1f039 WD	367	}
42d1f039 WD	368
42d1f039 WD	369	#if !defined(CONFIG_SPD_EEPROM)
	370	/*************************************************************************
	371	* fixed sdram init -- doesn't use serial presence detect.
	372	************************************************************************/
38dba0c2	373	phys_size_t fixed_sdram(void)
42d1f039	374	{
6d0f6bcf	375	#ifndef CONFIG_SYS_RAMBOOT
e76cd5d4	376	volatile ccsr_ddr_t ddr= (void )(CONFIG_SYS_MPC8xxx_DDR_ADDR);
6d0f6bcf JCPV	377
	378	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	379	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	380	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	381	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	382	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	383	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
42d1f039 WD	384	#if defined (CONFIG_DDR_ECC)
	385	ddr->err_disable = 0x0000000D;
	386	ddr->err_sbe = 0x00ff0000;
	387	#endif
	388	asm("sync;isync;msync");
	389	udelay(500);
	390	#if defined (CONFIG_DDR_ECC)
	391	/* Enable ECC checking */
6d0f6bcf	392	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL \| 0x20000000);
42d1f039	393	#else
6d0f6bcf	394	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
42d1f039 WD	395	#endif
	396	asm("sync; isync; msync");
	397	udelay(500);
	398	#endif
6d0f6bcf	399	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
42d1f039 WD	400	}
42d1f039 WD	401	#endif /* !defined(CONFIG_SPD_EEPROM) */
9aea9530 WD	402
	403
	404	#if defined(CONFIG_PCI)
	405	/*
	406	* Initialize PCI Devices, report devices found.
	407	*/
	408
	409	#ifndef CONFIG_PCI_PNP
	410	static struct pci_config_table pci_mpc85xxads_config_table[] = {
	411	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	412	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	413	pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	414	PCI_ENET0_MEMADDR,
	415	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER
	416	} },
	417	{ }
	418	};
	419	#endif
	420
	421
	422	static struct pci_controller hose = {
	423	#ifndef CONFIG_PCI_PNP
	424	config_table: pci_mpc85xxads_config_table,
	425	#endif
	426	};
	427
	428	#endif /* CONFIG_PCI */
	429
	430
	431	void
	432	pci_init_board(void)
	433	{
	434	#ifdef CONFIG_PCI
9aea9530 WD	435	pci_mpc85xx_init(&hose);
	436	#endif /* CONFIG_PCI */
	437	}
0e16387d MM	438
0e16387d MM	439
5ce71580	440	#if defined(CONFIG_OF_BOARD_SETUP)
0e16387d MM	441	void
	442	ft_board_setup(void blob, bd_t bd)
	443	{
5ce71580 KG	444	int node, tmp[2];
	445	const char *path;
	446
0e16387d	447	ft_cpu_setup(blob, bd);
5ce71580 KG	448
	449	node = fdt_path_offset(blob, "/aliases");
	450	tmp[0] = 0;
	451	if (node >= 0) {
	452	#ifdef CONFIG_PCI
	453	path = fdt_getprop(blob, node, "pci0", NULL);
	454	if (path) {
	455	tmp[1] = hose.last_busno - hose.first_busno;
	456	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	457	}
	458	#endif
	459	}
0e16387d MM	460	}
0e16387d MM	461	#endif